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[80.110.214.113]) by smtp.gmail.com with ESMTPSA id h14-20020a056402094e00b00559cc2082dcsm3577341edz.19.2024.01.19.01.40.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jan 2024 01:40:29 -0800 (PST) Date: Fri, 19 Jan 2024 10:40:26 +0100 From: rep.dot.nop@gmail.com To: Kito Cheng , "juzhe.zhong@rivai.ai" CC: "Kito.cheng" , jeffreyalaw , Robin Dapp , gcc-patches Subject: Re: [PATCH] RISC-V: Tweak the wording for the sorry message In-Reply-To: References: <20240119023457.1870618-1-kito.cheng@sifive.com> <59ABBD7F7EC1D927+2024011910352425760416@rivai.ai> Message-ID: <30359D73-87EE-45B5-A232-AF4AC011E481@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 19 January 2024 03:41:57 CET, Kito Cheng wrot= e: >Thanks, pushed to trunk :) Thanks, but don't you have to update the tests too, at least gcc/testsuite/gcc=2Etarget/riscv/rvv/base/big_endian-2=2Ec ? thanks > >On Fri, Jan 19, 2024 at 10:36=E2=80=AFAM juzhe=2Ezhong@rivai=2Eai > wrote: >> >> OK >> >> ________________________________ >> juzhe=2Ezhong@rivai=2Eai >> >> >> From: Kito Cheng >> Date: 2024-01-19 10:34 >> To: rep=2Edot=2Enop; jeffreyalaw; rdapp=2Egcc; juzhe=2Ezhong; gcc-patch= es >> CC: Kito Cheng >> Subject: [PATCH] RISC-V: Tweak the wording for the sorry message >> Use "does not" rather than "cannot", because it's implementation issue= =2E >> >> gcc/ChangeLog: >> >> * config/riscv/riscv=2Ecc (riscv_override_options_internal): Tweak >> sorry message=2E >> --- >> gcc/config/riscv/riscv=2Ecc | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/gcc/config/riscv/riscv=2Ecc b/gcc/config/riscv/riscv=2Ecc >> index f1d5129397f=2E=2Edd6e68a08c2 100644 >> --- a/gcc/config/riscv/riscv=2Ecc >> +++ b/gcc/config/riscv/riscv=2Ecc >> @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_opt= ions *opts) >> We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535=2E */ >> if (TARGET_MIN_VLEN_OPTS (opts) > 4096) >> - sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bi= t for " >> + sorry ("Current RISC-V GCC does not support VLEN greater than 4096= bit for " >> "'V' Extension"); >> /* FIXME: We don't support RVV in big-endian for now, we may enable = RVV with >> big-endian after finishing full coverage testing=2E */ >> if (TARGET_VECTOR && TARGET_BIG_ENDIAN) >> - sorry ("Current RISC-V GCC cannot support RVV in big-endian mode")= ; >> + sorry ("Current RISC-V GCC does not support RVV in big-endian mode= "); >> /* Convert -march to a chunks count=2E */ >> riscv_vector_chunks =3D riscv_convert_vector_bits (opts); >> -- >> 2=2E34=2E1 >> >>