From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 76446 invoked by alias); 4 Jun 2018 20:57:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 76435 invoked by uid 89); 4 Jun 2018 20:57:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:870 X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 04 Jun 2018 20:57:10 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 793CA81391; Mon, 4 Jun 2018 22:57:08 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3QeZcpIXU2bR; Mon, 4 Jun 2018 22:57:08 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 38E408138A; Mon, 4 Jun 2018 22:57:08 +0200 (CEST) From: Eric Botcazou To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, Richard Sandiford Subject: Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925) Date: Mon, 04 Jun 2018 20:57:00 -0000 Message-ID: <305632139.bEVa8srL7U@polaris> In-Reply-To: <94c0a64d9f0f94439db4e445507ddbb86dd3455e.1528115574.git.segher@kernel.crashing.org> References: <94c0a64d9f0f94439db4e445507ddbb86dd3455e.1528115574.git.segher@kernel.crashing.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-SW-Source: 2018-06/txt/msg00177.txt.bz2 > In the PR we have insns: > > Trying 23 -> 24: > 23: r123:SI=zero_extend(r122:HI) > REG_DEAD r122:HI > 24: [r115:SI]=r123:SI > REG_DEAD r123:SI > > which should be combined to > > (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A32]) > (and:SI (subreg:SI (reg:HI 122) 0) > (const_int 32767 [0x7fff]))) > > But nonzero_bits of reg:HI 122 is 0x7fff, and nonzero_bits1 thinks it > then also has that same nonzero_bits for the subreg. This is not > correct: the bit outside of HImode are undefined. load_extend_op > applies to loads from memory only, not anything else. Which means the > whole AND is optimised away. No, this is done on purpose for WORD_REGISTER_OPERATIONS targets and your patch will pessimize them. I'm going to have a look at the PR then. -- Eric Botcazou