From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 95301 invoked by alias); 9 Jun 2017 12:54:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 85226 invoked by uid 89); 9 Jun 2017 12:54:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=capable X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:24 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQk-0007ds-So for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:27 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQk-0007Te-9z for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 041A62B; Fri, 9 Jun 2017 05:54:22 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CBF63F3E1; Fri, 9 Jun 2017 05:54:21 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 18/30] [arm] Rewrite t-aprofile using new selector methodology Date: Fri, 09 Jun 2017 12:54:00 -0000 Message-Id: <308d75ef9451b050b791200d1e9788161ef72f48.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.7.4" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 X-SW-Source: 2017-06/txt/msg00627.txt.bz2 This is a multi-part message in MIME format. --------------2.7.4 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 1869 Now that the default FPU is 'auto' we can finally rewrite (and simplify) the rules for mapping compiler options to multilibs. We no-longer need to know the specific CPU, since the driver will construct a suitable -march flag for us; this greatly simplifies the overall logic. This patch rewrites the library list for A-profile cores. We use various Make extention rules to simplify the logic even further. A couple of minor tweaks to the configure script and to the main driver ensures that we always know the setting of -mfloat-abi and -marm/-mthumb. Again, this helps simplify the logic further. The change to arm_target_thumb_only relies on the fact that this routine is only called if neither -marm nor -mthumb has been previously selected or specified by the user. A new testsuite module is added to check the libraries generated. The new tests are only run if the compiler is configured with the relevant multilibs enabled. gcc * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm rather than NULL. * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. (all_feat_combs): New rule. (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework default libraries. * config/arm/t-aprofile: Rewrite. gcc/testsuite: gcc.target/arm/multilibs.exp: New file. --- gcc/common/config/arm/arm-common.c | 4 +- gcc/config.gcc | 4 +- gcc/config/arm/t-aprofile | 213 +++++++---------- gcc/config/arm/t-multilib | 48 ++-- gcc/testsuite/gcc.target/arm/multilib.exp | 381 ++++++++++++++++++++++++++= ++++ 5 files changed, 498 insertions(+), 152 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/multilib.exp --------------2.7.4 Content-Type: text/x-patch; name="0018-arm-Rewrite-t-aprofile-using-new-selector-methodolog.patch" Content-Disposition: attachment; filename="0018-arm-Rewrite-t-aprofile-using-new-selector-methodolog.patch" Content-Transfer-Encoding: quoted-printable Content-length: 49262 diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm= -common.c index 2188b77..be3f69f 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -215,7 +215,9 @@ arm_target_thumb_only (int argc, const char **argv) return "-mthumb"; } =20 - return NULL; + /* Compiler hasn't been configured with a default, and the CPU + doesn't require Thumb, so default to ARM. */ + return "-marm"; } =20 /* List the premitted CPU option names. If TARGET is a near miss for an diff --git a/gcc/config.gcc b/gcc/config.gcc index 8524a5f..b6dcbcd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3854,7 +3854,9 @@ case "${target}" in echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode = with --with-multilib-list=3D${with_multilib_list}" 1>&2 exit 1 fi - + # But pass the default value for float-abi + # through to the multilib selector + with_float=3D"soft" tmake_file=3D"${tmake_file} ${tmake_profile_file}" TM_MULTILIB_CONFIG=3D"$with_multilib_list" fi diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index b71cbda..2e3d4c8 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -24,147 +24,98 @@ # have their default values during the configure step. We enforce # this during the top-level configury. =20 +# Variables used later in this file. + +v7_a_nosimd_variants :=3D +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d1= 6 +vfpv4 +v7_a_simd_variants :=3D +simd +neon-fp16 +neon-vfpv4 +v7ve_nosimd_variants :=3D +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +f= p +vfpv4 +v7ve_vfpv3_simd_variants :=3D +neon +neon-fp16 +v7ve_vfpv4_simd_variants :=3D +simd +v8_a_nosimd_variants :=3D +crc +v8_a_simd_variants :=3D $(call all_feat_combs, simd crypto) +v8_1_a_simd_variants :=3D $(call all_feat_combs, simd crypto) +v8_2_a_simd_variants :=3D $(call all_feat_combs, simd fp16 crypto) + + # Arch and FPU variants to build libraries with =20 -MULTI_ARCH_OPTS_A =3D march=3Darmv7-a/march=3Darmv7ve/march=3Darmv8-a -MULTI_ARCH_DIRS_A =3D v7-a v7ve v8-a +MULTI_ARCH_OPTS_A =3D march=3Darmv7-a/march=3Darmv7-a+fp/march=3Darm= v7-a+simd/march=3Darmv7ve+simd/march=3Darmv8-a/march=3Darmv8-a+simd +MULTI_ARCH_DIRS_A =3D v7-a v7-a+fp v7-a+simd v7ve+simd v8-a v8-a+simd =20 -MULTI_FPU_OPTS_A =3D mfpu=3Dvfpv3-d16/mfpu=3Dneon/mfpu=3Dvfpv4-d16/= mfpu=3Dneon-vfpv4/mfpu=3Dneon-fp-armv8 -MULTI_FPU_DIRS_A =3D fpv3 simdv1 fpv4 simdvfpv4 simdv8 +# ARMv7-A - build nofp, fp-d16 and SIMD variants =20 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-a/mfloat-abi=3Dsoft +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-a+fp/mfloat-abi=3Dhard +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-a+fp/mfloat-abi=3Dsoftfp +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-a+simd/mfloat-abi=3Dhard +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-a+simd/mfloat-abi=3Dsoftfp =20 -# Option combinations to build library with +# ARMv7VE - only build a SIMD (+VFPv4) variant. +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7ve+simd/mfloat-abi=3Dhard +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7ve+simd/mfloat-abi=3Dsoftfp =20 -# Default CPU/Arch (ARM is implicitly included because it uses the default -# multilib) -MULTILIB_REQUIRED +=3D mthumb +# ARMv8-A - build nofp and SIMD variants. +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-a/mfloat-abi=3Dsoft +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-a+simd/mfloat-abi=3Dhard +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-a+simd/mfloat-abi=3Dsoftfp =20 -# ARMv7-A -MULTILIB_REQUIRED +=3D *march=3Darmv7-a -MULTILIB_REQUIRED +=3D *march=3Darmv7-a/mfpu=3Dvfpv3-d16/mfloat-abi= =3D* -MULTILIB_REQUIRED +=3D *march=3Darmv7-a/mfpu=3Dneon/mfloat-abi=3D* +# Matches =20 -# ARMv7VE -MULTILIB_REQUIRED +=3D *march=3Darmv7ve -MULTILIB_REQUIRED +=3D *march=3Darmv7ve/mfpu=3Dvfpv4-d16/mfloat-abi= =3D* -MULTILIB_REQUIRED +=3D *march=3Darmv7ve/mfpu=3Dneon-vfpv4/mfloat-abi= =3D* +# Arch Matches +# Map all v7-a FP variants to vfpv3-d16 (+fp) +MULTILIB_MATCHES +=3D $(foreach ARCH, $(filter-out +fp, $(v7_a_nosimd_vari= ants)), \ + march?armv7-a+fp=3Dmarch?armv7-a$(ARCH)) =20 -# ARMv8-A -MULTILIB_REQUIRED +=3D *march=3Darmv8-a -MULTILIB_REQUIRED +=3D *march=3Darmv8-a/mfpu=3Dneon-fp-armv8/mfloat-a= bi=3D* +# Map all v7-a SIMD variants to neon-vfpv3 (+simd) +MULTILIB_MATCHES +=3D $(foreach ARCH, $(filter-out +simd, $(v7_a_simd_vari= ants)), \ + march?armv7-a+simd=3Dmarch?armv7-a$(ARCH)) =20 +# Neither FP nor SIMD: map v7ve to v7-a +MULTILIB_MATCHES +=3D march?armv7-a=3Dmarch?armv7ve =20 -# Matches +# ARMv7ve FP-only variants: map down to v7-a+fp +MULTILIB_MATCHES +=3D $(foreach ARCH, $(v7ve_nosimd_variants), \ + march?armv7-a+fp=3Dmarch?armv7ve$(ARCH)) =20 -# CPU Matches -MULTILIB_MATCHES +=3D march?armv7-a=3Dmcpu?marvell-pj4 -MULTILIB_MATCHES +=3D march?armv7-a=3Dmcpu?generic-armv7-a -MULTILIB_MATCHES +=3D march?armv7-a=3Dmcpu?cortex-a8 -MULTILIB_MATCHES +=3D march?armv7-a=3Dmcpu?cortex-a9 -MULTILIB_MATCHES +=3D march?armv7-a=3Dmcpu?cortex-a5 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a7 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a15 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a12 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a17 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a15.cortex-a7 -MULTILIB_MATCHES +=3D march?armv7ve=3Dmcpu?cortex-a17.cortex-a7 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a32 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a35 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a53 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a57 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a57.cortex-a53 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a72 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a72.cortex-a53 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a73 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a73.cortex-a35 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?cortex-a73.cortex-a53 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?exynos-m1 -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?falkor -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?qdf24xx -MULTILIB_MATCHES +=3D march?armv8-a=3Dmcpu?xgene1 +# ARMv7ve with SIMD, but SIMD is less capable than the default - map down = to v7-a+simd +MULTILIB_MATCHES +=3D $(foreach ARCH, $(v7ve_vfpv3_simd_variants), \ + march?armv7-a+simd=3Dmarch?armv7ve$(ARCH)) =20 -# Arch Matches -MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8-a+crc -MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.1-a -MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.1-a+crc -MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.2-a -MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.2-a+fp16 - -# FPU matches -MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3 -MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3-fp16 -MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3-d16-fp16 -MULTILIB_MATCHES +=3D mfpu?neon=3Dmfpu?neon-fp16 -MULTILIB_MATCHES +=3D mfpu?vfpv4-d16=3Dmfpu?vfpv4 -MULTILIB_MATCHES +=3D mfpu?vfpv4-d16=3Dmfpu?fpv5-d16 -MULTILIB_MATCHES +=3D mfpu?vfpv4-d16=3Dmfpu?fp-armv8 -MULTILIB_MATCHES +=3D mfpu?neon-fp-armv8=3Dmfpu?crypto-neon-fp-armv8 -MULTILIB_MATCHES +=3D mfpu?vfp=3Dmfpu?vfpv2 -MULTILIB_MATCHES +=3D mfpu?neon=3Dmfpu?neon-vfpv3 - - -# Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a. -# So if new CPUs are added above at the newer architecture levels, -# do something to map them below here. -# We take the approach of mapping down to v7-a regardless of what -# the fp option is if the integer architecture brings things down. -# This applies to any similar combination at the v7ve and v8-a arch -# levels. - -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=3Dm= arch.armv7ve/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp= =3Dmarch.armv7ve/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=3Dm= arch.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp= =3Dmarch.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=3Dm= arch.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp= =3Dmarch.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.hard=3Dmarch.= armv7ve/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.softfp=3Dmarc= h.armv7ve/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.hard=3Dmarch.= armv8-a/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.softfp=3Dmarc= h.armv8-a/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.hard=3Dmarch.= armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.softfp=3Dmarc= h.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.hard=3Dmarch.= armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7-a/mfpu.neon/mfloat-abi.softfp=3Dmarc= h.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=3Dm= arch.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp= =3Dmarch.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=3D= march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp= =3Dmarch.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE +=3D march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=3D= march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE +=3D march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp= =3Dmarch.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.softfp - - - -# And again for mthumb. - -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.h= ard=3Dmthumb/march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.s= oftfp=3Dmthumb/march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.h= ard=3Dmthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.s= oftfp=3Dmthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.h= ard=3Dmthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.s= oftfp=3Dmthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard= =3Dmthumb/march.armv7ve/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp= =3Dmthumb/march.armv7ve/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard= =3Dmthumb/march.armv8-a/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp= =3Dmthumb/march.armv8-a/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard= =3Dmthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp= =3Dmthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard= =3Dmthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp= =3Dmthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.h= ard=3Dmthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.s= oftfp=3Dmthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.= hard=3Dmthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.= softfp=3Dmthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.= hard=3Dmthumb/march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE +=3D mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.= softfp=3Dmthumb/march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.softfp +# ARMv8 without SIMD: map down to base architecture +MULTILIB_MATCHES +=3D $(foreach ARCH, $(v8_a_nosimd_variants), \ + march?armv8-a=3Dmarch?armv8-a$(ARCH)) + +# ARMv8 with SIMD: map down to base arch + simd +MULTILIB_MATCHES +=3D march?armv8-a+simd=3Dmarch?armv8-a+crc+simd \ + $(foreach ARCH, $(filter-out +simd, $(v8_a_simd_variants)), \ + march?armv8-a+simd=3Dmarch?armv8-a$(ARCH) \ + march?armv8-a+simd=3Dmarch?armv8-a+crc$(ARCH)) + +# Baseline v8.1-a: map down to baseline v8-a +MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.1-a + +# Map all v8.1-a SIMD variants to v8-a+simd +MULTILIB_MATCHES +=3D $(foreach ARCH, $(v8_1_a_simd_variants), \ + march?armv8-a+simd=3Dmarch?armv8.1-a$(ARCH)) + +# Baseline v8.2-a: map down to baseline v8-a +MULTILIB_MATCHES +=3D march?armv8-a=3Dmarch?armv8.2-a + +# Map all v8.2-a SIMD variants to v8-a+simd +MULTILIB_MATCHES +=3D $(foreach ARCH, $(v8_2_a_simd_variants), \ + march?armv8-a+simd=3Dmarch?armv8.2-a$(ARCH)) + +# Use Thumb libraries for everything. + +MULTILIB_REUSE +=3D mthumb/march.armv7-a/mfloat-abi.soft=3Dmarm/march.arm= v7-a/mfloat-abi.soft + +MULTILIB_REUSE +=3D mthumb/march.armv8-a/mfloat-abi.soft=3Dmarm/march.arm= v8-a/mfloat-abi.soft + +MULTILIB_REUSE +=3D $(foreach ABI, hard softfp, \ + $(foreach ARCH, armv7-a+fp armv7-a+simd armv7ve+simd armv8-a+simd,= \ + mthumb/march.$(ARCH)/mfloat-abi.$(ABI)=3Dmarm/march.$(ARCH)/mflo= at-abi.$(ABI))) + +# Softfp but no FP, use the soft-float libraries. +MULTILIB_REUSE +=3D $(foreach MODE, arm thumb, \ + $(foreach ARCH, armv7-a armv8-a, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=3Dm$(MODE)/march.$(ARCH)/mf= loat-abi.softfp)) diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 642e731..77ce762 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -29,6 +29,7 @@ MULTILIB_DIRNAMES =3D MULTILIB_EXCEPTIONS =3D MULTILIB_MATCHES =3D MULTILIB_REUSE =3D +MULTILIB_REQUIRED =3D =20 comma :=3D , tm_multilib_list :=3D $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) @@ -36,6 +37,26 @@ tm_multilib_list :=3D $(subst $(comma), ,$(TM_MULTILIB_C= ONFIG)) HAS_APROFILE :=3D $(filter aprofile,$(tm_multilib_list)) HAS_RMPROFILE :=3D $(filter rmprofile,$(tm_multilib_list)) =20 +# Produce the combinatorial list of extensions. Where there are +# multiple permutations for a combination, the ordering is the +# selected by the forward ordering of the original list. This matches +# the canonical ordering generated by the canonicalizer in the driver. +# +# For example, +# $(call all_feat_combs, a b) +# will produce +# +a +a+b +b +# but will not include +# +b+a +# The rule is recursive and can be called with any (reasonable) list of +# extensions. +all_feat_combs =3D +$(firstword $(1)) \ + $(if $(wordlist 2, $(words $(1)), $(1)), \ + $(foreach OPT, \ + $(call all_feat_combs, \ + $(wordlist 2, $(words $(1)), $(1))), \ + +$(firstword $(1))$(OPT) $(OPT)),) + ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile endif @@ -45,25 +66,14 @@ endif SEP :=3D $(and $(HAS_APROFILE),$(HAS_RMPROFILE),/) =20 =20 -# We have the following hierachy: -# ISA: A32 (.) or T16/T32 (thumb) -# Architecture: ARMv6-M (v6-m), ARMv7-M (v7-m), ARMv7E-M (v7e-m), -# ARMv7 (v7-ar), ARMv7-A (v7-a), ARMv7VE (v7ve), -# ARMv8-M Baseline (v8-m.base), ARMv8-M Mainline (v8-m.mai= n) -# or ARMv8-A (v8-a). -# FPU: VFPv3-D16 (fpv3), NEONv1 (simdv1), FPV4-SP-D16 (fpv4-sp), -# VFPv4-D16 (fpv4), NEON-VFPV4 (simdvfpv4), FPV5-SP-D16 (fpv5-sp), -# VFPv5-D16 (fpv5), NEON for ARMv8 (simdv8), or None (.). -# Float-abi: Soft (.), softfp (softfp), or hard (hard). - -MULTILIB_OPTIONS +=3D mthumb -MULTILIB_DIRNAMES +=3D thumb +MULTILIB_OPTIONS +=3D marm/mthumb +MULTILIB_DIRNAMES +=3D arm thumb =20 -MULTILIB_OPTIONS +=3D $(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) -MULTILIB_DIRNAMES +=3D $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) +MULTILIB_OPTIONS +=3D march=3Darmv5te+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$= (MULTI_ARCH_OPTS_RM) +MULTILIB_DIRNAMES +=3D v5te $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) =20 -MULTILIB_OPTIONS +=3D $(MULTI_FPU_OPTS_A)$(SEP)$(MULTI_FPU_OPTS_RM) -MULTILIB_DIRNAMES +=3D $(MULTI_FPU_DIRS_A) $(MULTI_FPU_DIRS_RM) +MULTILIB_OPTIONS +=3D mfloat-abi=3Dsoft/mfloat-abi=3Dsoftfp/mfloat-a= bi=3Dhard +MULTILIB_DIRNAMES +=3D nofp softfp hard =20 -MULTILIB_OPTIONS +=3D mfloat-abi=3Dsoftfp/mfloat-abi=3Dhard -MULTILIB_DIRNAMES +=3D softfp hard +MULTILIB_REQUIRED +=3D mthumb/mfloat-abi=3Dsoft +MULTILIB_REQUIRED +=3D marm/march=3Darmv5te+fp/mfloat-abi=3Dhard diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.= target/arm/multilib.exp new file mode 100644 index 0000000..bef5be8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -0,0 +1,381 @@ +# Copyright (C) 2017 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +#=20 +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#=20 +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +load_lib gcc-dg.exp + +dg-init + +if { [board_info [target_info name] exists multilib_flags]=20 + && [regexp {(-marm|-mthumb|-march=3D.*|-mcpu=3D.*|-mfpu=3D.*|-mfloat= =3Dabi=3D.*)\y} [board_info [target_info name] multilib_flags]] } { +=09 + # Multilib flags override anything we can apply to a test, so + # skip if any of the above options are set there. + verbose "skipping multilib tests due to multilib_flags setting" 1 + return +} + +# We don't want to run this test multiple times in a parallel make check. +if ![gcc_parallel_test_run_p options] { + return +} +gcc_parallel_test_enable 0 + +proc multilib_config {profile} { + return [check_configured_with [join [list {with-multilib-list=3D([^ ]+= ,)?} $profile {(,[^ ]+)?}] ""]] +} + +proc check_multi_dir { gcc_opts multi_dir } { + global tool + + set gcc_output [${tool}_target_compile "--print-multi-directory $gcc_o= pts" "" "none" ""] + if { [string match "$multi_dir\n" $gcc_output] } { + pass "multilibdir $gcc_opts $multi_dir" + } else { + fail "multilibdir $gcc_opts $multi_dir" + } +} + +if {[multilib_config "aprofile"] } { + foreach {opts dir} { + {-mcpu=3Dcortex-a8 -mfloat-abi=3Dsoft} "thumb/v7-a/nofp" + {-mcpu=3Dcortex-a8 -mfloat-abi=3Dsoftfp} "thumb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfloat-abi=3Dhard} "thumb/v7-a+simd/hard" + {-mcpu=3Dcortex-a15} "thumb/v7-a/nofp" + {-mcpu=3Dcortex-a15 -mfloat-abi=3Dhard} "thumb/v7ve+simd/hard" + {-mcpu=3Dcortex-a15 -marm -mfloat-abi=3Dhard} "thumb/v7ve+simd/har= d" + {-mcpu=3Dcortex-a15 -mthumb -mfloat-abi=3Dhard} "thumb/v7ve+simd/h= ard" + {-mcpu=3Dcortex-a7+nosimd -mfloat-abi=3Dhard} "thumb/v7-a+fp/hard" + {-mcpu=3Dcortex-a7+nofp -mfloat-abi=3Dsoftfp} "thumb/v7-a/nofp" + {-mcpu=3Dgeneric-armv7-a+vfpv4 -mfloat-abi=3Dsoftfp} "thumb/v7-a+fp/softf= p" + {-march=3Darmv7ve+vfpv3 -mfloat-abi=3Dhard} "thumb/v7-a+fp/hard" + {-march=3Darmv7ve -mfloat-abi=3Dsoftfp -mfpu=3Dneon} "thumb/v7-a+simd/sof= tfp" + {-march=3Darmv7ve -mfloat-abi=3Dsoftfp -mfpu=3Dneon-vfpv4} "thumb/v7ve+si= md/softfp" + {-march=3Darmv7ve -mfloat-abi=3Dsoftfp -mfpu=3Dvfpv4} "thumb/v7-a+fp/soft= fp" + {-march=3Darmv8-a+crc+simd -mfloat-abi=3Dsoft} "thumb/v8-a/nofp" + {-march=3Darmv8-a+crc+simd -mfloat-abi=3Dsoftfp} "thumb/v8-a+simd/softfp" + {-march=3Darmv8.1-a+crypto -mfloat-abi=3Dsoft} "thumb/v8-a/nofp" + {-march=3Darmv8.1-a+crypto -mfloat-abi=3Dsoftfp} "thumb/v8-a+simd/softfp" + {-march=3Darmv8.2-a+crypto -mfloat-abi=3Dsoft} "thumb/v8-a/nofp" + {-march=3Darmv8.2-a+simd+crypto -mfloat-abi=3Dsoftfp} "thumb/v8-a+simd/so= ftfp" + {-march=3Darmv8.2-a+simd+crypto+nofp -mfloat-abi=3Dsoftfp} "thumb/v8-a/no= fp" + {-march=3Darmv8.2-a+simd+nofp+crypto -mfloat-abi=3Dsoftfp} "thumb/v8-a+si= md/softfp" + {-mcpu=3Dcortex-a53+crypto -mfloat-abi=3Dhard} "thumb/v8-a+simd/hard" + {-mcpu=3Dcortex-a53+nofp -mfloat-abi=3Dsoftfp} "thumb/v8-a/nofp" + {-march=3Darmv8-a+crc -mfloat-abi=3Dhard -mfpu=3Dvfp} "thumb/v8-a+simd/ha= rd" + {-march=3Darmv8-a+crc+simd -mfloat-abi=3Dsoft -mfpu=3Dneon} "thumb/v8-a/n= ofp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v8= -a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thum= b/v7-a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thum= b/v7-a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thum= b/v7-a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thum= b/v7-a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thu= mb/v7-a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thu= mb/v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+f= p/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v8-a+s= imd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v8= -a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp= /hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+f= p/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v8-a+s= imd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+sim= d/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+sim= d/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+sim= d/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+sim= d/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+si= md/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v8-a+si= md/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7= -a+simd/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7= -a+simd/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7= -a+simd/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7= ve+simd/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v= 7ve+simd/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v= 8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v8-= a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb= /v7-a+simd/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb= /v7-a+simd/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb= /v7-a+simd/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb= /v7ve+simd/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thum= b/v7ve+simd/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thum= b/v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/= v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "th= umb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "th= umb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "th= umb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "th= umb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "t= humb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "t= humb/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a= +fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a= +simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/= v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a= +fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a= +simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+s= imd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+s= imd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+s= imd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+s= imd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+= simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a+= simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7-a+simd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7-a+simd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7-a+simd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/= v7ve+simd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb= /v7ve+simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb= /v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v7ve+simd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "th= umb/v7ve+simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "th= umb/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -marm} "thumb/v8-a= +simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v8= -a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thumb= /v7-a+fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -marm} "thumb= /v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v7-a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -marm} "thu= mb/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp/= hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -marm} "thumb/v8-a+sim= d/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+f= p/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a+s= imd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v7-a= +fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -marm} "thumb/v8-a= +simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v7= -a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -marm} "thumb/v8= -a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-a+fp/= hard" + {-march=3Darmv8-a -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -marm} "thumb/v8-a+sim= d/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+f= p/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a+s= imd/softfp" + {-march=3Darmv7-a -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v7-a+simd= /hard" + {-march=3Darmv8-a -mfpu=3Dneon -mfloat-abi=3Dhard -marm} "thumb/v8-a+simd= /hard" + {-march=3Darmv7-a -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v7-a+si= md/softfp" + {-march=3Darmv8-a -mfpu=3Dneon -mfloat-abi=3Dsoftfp -marm} "thumb/v8-a+si= md/softfp" + {-march=3Darmv7-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v7-= a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -marm} "thumb/v8-= a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -marm} "thumb/v= 8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v7-a+= fp/hard" + {-march=3Darmv8-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -marm} "thumb/v8-a+= simd/hard" + {-march=3Darmv7-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v7-= a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -marm} "thumb/v8-= a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb/= v7-a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -marm} "thumb/= v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thum= b/v7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -marm} "thum= b/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dhard -marm} = "thumb/v7-a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dhard -marm} = "thumb/v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dsoftfp -marm= } "thumb/v7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dsoftfp -marm= } "thumb/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/= v7-a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/= v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "th= umb/v7-a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "th= umb/v7-a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "th= umb/v7-a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "th= umb/v7-a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "t= humb/v7-a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "t= humb/v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v8-a= +simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/= v7-a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/= v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a= +fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v8-a= +simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+s= imd/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+s= imd/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+s= imd/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+s= imd/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+= simd/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v8-a+= simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/= v7-a+simd/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/= v7-a+simd/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/= v7-a+simd/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/= v7ve+simd/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb= /v7ve+simd/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb= /v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+fp/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v= 8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thu= mb/v7-a+simd/hard" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thu= mb/v7-a+simd/hard" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thu= mb/v7-a+simd/hard" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thu= mb/v7ve+simd/hard" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "th= umb/v7ve+simd/hard" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "th= umb/v8-a+simd/hard" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} = "thumb/v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} = "thumb/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8= -a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7= -a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8= -a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +simd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +simd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +simd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +simd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-= a+simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8-= a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7-a+simd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7-a+simd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7-a+simd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thum= b/v7ve+simd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thu= mb/v7ve+simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thu= mb/v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+fp/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v8-a+simd/softfp" + {-mcpu=3Dcortex-a8 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a5 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a9 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v7-a+simd/softfp" + {-mcpu=3Dcortex-a7 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v7ve+simd/softfp" + {-mcpu=3Dcortex-a15 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v7ve+simd/softfp" + {-mcpu=3Dcortex-a53 -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "= thumb/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v8= -a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "thu= mb/v7-a+fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dhard -mthumb} "thu= mb/v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v7-a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3-d16-fp16 -mfloat-abi=3Dsoftfp -mthumb} "t= humb/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+f= p/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv3 -mfloat-abi=3Dhard -mthumb} "thumb/v8-a+s= imd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv3 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8-a= +simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v7= -a+fp/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dhard -mthumb} "thumb/v8= -a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v7-a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv4-d16 -mfloat-abi=3Dsoftfp -mthumb} "thumb/= v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+f= p/hard" + {-march=3Darmv8-a -mfpu=3Dvfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v8-a+s= imd/hard" + {-march=3Darmv7-a -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a= +fp/softfp" + {-march=3Darmv8-a -mfpu=3Dvfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8-a= +simd/softfp" + {-march=3Darmv7-a -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v7-a+si= md/hard" + {-march=3Darmv8-a -mfpu=3Dneon -mfloat-abi=3Dhard -mthumb} "thumb/v8-a+si= md/hard" + {-march=3Darmv7-a -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v7-a+= simd/softfp" + {-march=3Darmv8-a -mfpu=3Dneon -mfloat-abi=3Dsoftfp -mthumb} "thumb/v8-a+= simd/softfp" + {-march=3Darmv7-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v= 7-a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dhard -mthumb} "thumb/v= 8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dneon-vfpv4 -mfloat-abi=3Dsoftfp -mthumb} "thumb= /v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v7-= a+fp/hard" + {-march=3Darmv8-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dhard -mthumb} "thumb/v8-= a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v= 7-a+fp/softfp" + {-march=3Darmv8-a -mfpu=3Dfp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "thumb/v= 8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thum= b/v7-a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dhard -mthumb} "thum= b/v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "th= umb/v7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dneon-fp-armv8 -mfloat-abi=3Dsoftfp -mthumb} "th= umb/v8-a+simd/softfp" + {-march=3Darmv7-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dhard -mthumb= } "thumb/v7-a+simd/hard" + {-march=3Darmv8-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dhard -mthumb= } "thumb/v8-a+simd/hard" + {-march=3Darmv7-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dsoftfp -mthu= mb} "thumb/v7-a+simd/softfp" + {-march=3Darmv8-a -mfpu=3Dcrypto-neon-fp-armv8 -mfloat-abi=3Dsoftfp -mthu= mb} "thumb/v8-a+simd/softfp" + } { + check_multi_dir $opts $dir + } +} + +gcc_parallel_test_enable 1 + --------------2.7.4--