From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 8028A385700C for ; Mon, 14 Aug 2023 06:10:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8028A385700C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3CE68300089; Mon, 14 Aug 2023 06:10:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1691993449; bh=kqEnJXrLO7yIguohWhCrk3AyRSjoVDg2yT0qpjqNEFE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=ihUZa8E0IlYWWkixvfksxCzYD0EwVUf1Xy/kaiq6SfSzk95XH+5PSommFWS2pscWG dyPkZ2vehrBF7w4IL3aqIAoCBFRMb+/EoZSoWom5bgx5r+NRuIm7wc5dQMeUdTJ4i3 1puAzwJIHE1VasZHGP9CIrbzH0TDqKnitliD5Tl0= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH v2 3/3] RISC-V: Add stub support for existing extensions (unprivileged) Date: Mon, 14 Aug 2023 06:09:53 +0000 Message-ID: <3091a5d106d2d8256723c6a74f08f8607c9f019f.1691993380.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects, GCC should support almost all extensions that Binutils support, even if the GCC does not touch a thing. This commit adds stub supported standard unprivileged extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet merged 'Zce', 'Zcmp' and 'Zcmt' support). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from unprivileged extensions. (riscv_ext_version_table): Add stub support for all unprivileged extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-31.c: New test for a stub unprivileged extension 'Zcb' with some implications. --- gcc/common/config/riscv/riscv-common.cc | 24 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0c351105e015..27e9072899bf 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -121,6 +121,20 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvksg", "zvks"}, {"zvksg", "zvkg"}, + {"zcb", "zca"}, + {"zcd", "zca"}, + {"zcd", "d"}, + {"zcf", "zca"}, + {"zcf", "f"}, + {"zce", "zca"}, + {"zce", "zcb"}, + {"zce", "zcmp"}, + {"zce", "zcmt"}, + {"zcmp", "zca"}, + {"zcmt", "zca"}, + {"zcmt", "zcicsr"}, + + {"zfa", "f"}, {"zfh", "zfhmin"}, {"zfhmin", "f"}, {"zvfhmin", "zve32f"}, @@ -197,6 +211,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zca", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zce", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcf", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -219,6 +241,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0}, {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, @@ -265,6 +288,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfa", ISA_SPEC_CLASS_NONE, 0, 1}, {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c b/gcc/testsuite/gcc.target/riscv/predef-31.c new file mode 100644 index 000000000000..4ea11442f995 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-31.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000)) +#error "__riscv_i" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if !defined(__riscv_zca) +#error "__riscv_zca" +#endif + +#if !defined(__riscv_zcb) +#error "__riscv_zcb" +#endif + + return 0; +} -- 2.41.0