From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 4E9A73858D28 for ; Mon, 20 May 2024 21:46:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4E9A73858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4E9A73858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=83.149.199.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716241600; cv=none; b=seFFtz4wTnNNaGmWFFbvTr4+d0m7HynfnssyHPNA0kzfbGnGUvYNBHfB4voxbEgrum/cJV4Q1tMknBsrK1r35Z62cxSjPteuct8WLfIM8xeklKu29NNtQE+XBi5dejpJXPKe8Ye1Ax0/XhLSpTeuAZwad7TlTe4L2gpu06AA6Wk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716241600; c=relaxed/simple; bh=lxQ4/qnXRA+hulmfOso3qhZYxeTggrBpu/AM4pcLjWI=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=Ti9ipeAyIhiom2ut06C+h4IYd6xu9ylK32SpNfoh0pq8F9aPoZQ0z3frV/bxaS8TBaX3XZRrNdEus1/VWOorYkHfGKc5YhTqU0b4XPdPUlhnK/GVhIcMJEKmJ7h8V5uBrOJNNvrE/BO7Wuol9txhWPLdtCXQ+x/x+g3xxD89hs4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [10.10.3.121] (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTPS id A940C4076721; Mon, 20 May 2024 21:46:36 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru A940C4076721 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1716241596; bh=7VZueaDMSAzV9AKhqcmo3Rcx9ro+v/u6XST+MO37DYM=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=MuhGOC82WdFZTarLrf0eogw1xxUOciJvXNHg+ZcrIPxTLbiHetL/MXvCXl2+67/BX oegAKHCJFu83mH0LVqSTLDd7z4Q4KkBR/qyJaWePFogpqCtrZGwU0rKy7dRoNylgGZ kGzfClM+62Pa0thjDWhrvFJokkZ8Sya0gcWh3mxk= Date: Tue, 21 May 2024 00:46:36 +0300 (MSK) From: Alexander Monakov To: Roger Sayle cc: 'Hongtao Liu' , gcc-patches@gcc.gnu.org, 'Uros Bizjak' Subject: Re: [x86 SSE] Improve handling of ternlog instructions in i386/sse.md (v2) In-Reply-To: <001801daa896$39a7a5e0$acf6f1a0$@nextmovesoftware.com> Message-ID: <30a14f25-c566-db2b-6453-fc347939a584@ispras.ru> References: <001801daa4b7$62d704c0$28850e40$@nextmovesoftware.com> <001801daa896$39a7a5e0$acf6f1a0$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-0.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MEDICAL_SUBJECT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello! I looked at ternlog a bit last year, so I'd like to offer some drive-by comments. If you want to tackle them in a follow-up patch, or leave for someone else to handle, please let me know. On Fri, 17 May 2024, Roger Sayle wrote: > This revised patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=unix{-m32} > with no new failures. Ok for mainline? Just to make sure: no new tests for the new tricks? > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > +/* Determine the ternlog immediate index that implements 3-operand > + ternary logic expression OP. This uses and modifies the 3 element > + array ARGS to record and check the leaves, either 3 REGs, or 2 REGs > + and MEM. Returns an index between 0 and 255 for a valid ternlog, > + or -1 if the expression isn't suitable. */ > + > +int > +ix86_ternlog_idx (rtx op, rtx *args) > +{ > + int idx0, idx1; > + > + if (!op) > + return -1; > + > + switch (GET_CODE (op)) > + { > + case REG: > + if (!args[0]) > + { > + args[0] = op; > + return 0xf0; >From readability perspective, I wonder if it's nicer to have something like enum { TERNLOG_A = 0xf0, TERNLOG_B = 0xcc, TERNLOG_C = 0xaa } and then use them to build the immediates. > + } > + if (REGNO (op) == REGNO (args[0])) > + return 0xf0; > + if (!args[1]) > + { > + args[1] = op; > + return 0xcc; > + } [snip] > + > +/* Return TRUE if OP (in mode MODE) is the leaf of a ternary logic > + expression, such as a register or a memory reference. */ > + > +bool > +ix86_ternlog_leaf_p (rtx op, machine_mode mode) > +{ > + /* We can't use memory_operand here, as it may return a different > + value before and after reload (for volatile MEMs) which creates > + problems splitting instructions. */ > + return register_operand (op, mode) > + || MEM_P (op) > + || GET_CODE (op) == CONST_VECTOR > + || bcst_mem_operand (op, mode); Did your editor automatically indent this correctly for you? I think usually such expressions have outer parenthesis. > +} [snip] > +/* Expand a 3-operand ternary logic expression. Return TARGET. */ > +rtx > +ix86_expand_ternlog (machine_mode mode, rtx op0, rtx op1, rtx op2, int idx, > + rtx target) > +{ > + rtx tmp0, tmp1, tmp2; > + > + if (!target) > + target = gen_reg_rtx (mode); > + > + /* Canonicalize ternlog index for degenerate (duplicated) operands. */ But this only canonicalizes the case of triplicated operands, and does nothing if two operands are duplicates of each other, and the third is distinct. Handling that would complicate the already large patch a lot though. > + if (rtx_equal_p (op0, op1) && rtx_equal_p (op0, op2)) > + switch (idx & 0x81) > + { > + case 0x00: > + idx = 0x00; > + break; > + case 0x01: > + idx = 0x0f; > + break; > + case 0x80: > + idx = 0xf0; > + break; > + case 0x81: > + idx = 0xff; > + break; > + } > + > + switch (idx & 0xff) > + { > + case 0x00: > + if ((!op0 || !side_effects_p (op0)) > + && (!op1 || !side_effects_p (op1)) > + && (!op2 || !side_effects_p (op2))) > + { > + emit_move_insn (target, CONST0_RTX (mode)); > + return target; > + } > + break; > + > + case 0x0a: /* ~a&c */ With the enum idea above, this could be 'case ~TERNLOG_A & TERNLOG_C', etc. Alexander