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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 kito.cheng <kito.cheng@gmail.com>,
	 Kito.cheng <kito.cheng@sifive.com>,
	 jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
Date: Tue, 7 Nov 2023 20:11:12 +0800	[thread overview]
Message-ID: <31EEC5502A61CBA7+202311072011123340987@rivai.ai> (raw)
In-Reply-To: <bc35c430-c0d3-4024-bcdd-488259891f68@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 687 bytes --]

Thanks. Committed.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-11-07 20:10
To: juzhe.zhong@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add RISC-V into vect_cmdline_needed
> It need command line to enable SIMD auto-vectorization (VLS mode in RVV).
> It will enable VLS modes auto-vectorization by default if we didn't add RISCV into vect_cmdline.
> So adding it to disable VLS mode vectorization which will fix the FAILs like other targets.
 
Ah so it's about SIMD despite the name, I see.  Still weird
but adding riscv then makes sense.  So OK.  The test probably
just very old.
 
Regards
Robin
 

      reply	other threads:[~2023-11-07 12:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-07 11:48 Juzhe-Zhong
2023-11-07 12:04 ` Robin Dapp
2023-11-07 12:07   ` juzhe.zhong
2023-11-07 12:10     ` Robin Dapp
2023-11-07 12:11       ` juzhe.zhong [this message]

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