From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 00A4838303E6 for ; Mon, 6 Jun 2022 22:05:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 00A4838303E6 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 256KTsYV017324; Mon, 6 Jun 2022 22:05:58 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghn4r5mvt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:57 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 256M0gVP028579; Mon, 6 Jun 2022 22:05:57 GMT Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com [169.55.85.253]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghn4r5mvj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:57 +0000 Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1]) by ppma01wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 256LobOp013995; Mon, 6 Jun 2022 22:05:56 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma01wdc.us.ibm.com with ESMTP id 3gfy19g8r1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:56 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 256M5t8t45482476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 22:05:55 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 83AC2AC062; Mon, 6 Jun 2022 22:05:55 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 22441AC05E; Mon, 6 Jun 2022 22:05:55 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:05:55 +0000 (GMT) Message-ID: <31e048ac4602cc12e99889a0b42559c25b17604a.camel@vnet.ibm.com> Subject: [PATCH, RS6000 3/5] Rework the RS6000_BTM defines, continued. From: will schmidt To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool , David Edelsohn , "Kewen.Lin" Date: Mon, 06 Jun 2022 17:05:54 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YWqDUVK6UUR5vkVrgadqV-VRLsQRRSmI X-Proofpoint-GUID: gltnxEzV7l6kCotQoGoHZB_Ya76OJx_Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 mlxlogscore=960 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2022 22:06:01 -0000 [PATCH, RS6000 3/5] Rework the RS6000_BTM defines, continued. The RS6000_BTM_ definitions are mostly unused after the rs6000 builtin code was reworked. This cleans up the remaining RS6000_BTM_ references by replacing them with their OPTION_MASK_ equivalents. This patch removes the defines RS6000_BTM_MODULO, RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_CRYPTO, RS6000_BTM_HTM, RS6000_BTM_FRE. gcc/ * config/rs6000/rs6000.cc (RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_FRE, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_MODULO, RS6000_BTM_CRYPTO, RS6000_BTM_HTM): Replace with OPTION_MASK_ALTIVEC, OPTION_MASK_CMPB, OPTION_MASK_VSX, OPTION_MASK_POPCNTB, OPTION_MASK_P8_VECTOR, OPTION_MASK_P9_VECTOR, OPTION_MASK_P9_MISC, OPTION_MASK_MODULO, OPTION_MASK_CRYPTO, OPTION_MASK_HTM. * config/rs6000/rs6000.h (RS6000_BTM_MODULO, RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_CRYPTO, RS6000_BTM_HTM, RS6000_BTM_FRE): Remove. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 253110910bfa..6b7a6db9a445 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3377,27 +3377,27 @@ darwin_rs6000_override_options (void) bits, and some options are no longer in target_flags. */ HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) + return (((TARGET_ALTIVEC) ? OPTION_MASK_ALTIVEC : 0) + | ((TARGET_CMPB) ? OPTION_MASK_CMPB : 0) + | ((TARGET_VSX) ? OPTION_MASK_VSX : 0) + | ((TARGET_FRE) ? OPTION_MASK_POPCNTB : 0) | ((TARGET_FRES) ? OPTION_MASK_PPC_GFXOPT : 0) | ((TARGET_FRSQRTE) ? OPTION_MASK_PPC_GFXOPT : 0) | ((TARGET_FRSQRTES) ? OPTION_MASK_POPCNTB : 0) | ((TARGET_POPCNTD) ? OPTION_MASK_POPCNTD : 0) | ((rs6000_cpu == PROCESSOR_CELL) ? OPTION_MASK_FPRND : 0) - | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) - | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) - | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) - | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) + | ((TARGET_P8_VECTOR) ? OPTION_MASK_P8_VECTOR : 0) + | ((TARGET_P9_VECTOR) ? OPTION_MASK_P9_VECTOR : 0) + | ((TARGET_P9_MISC) ? OPTION_MASK_P9_MISC : 0) + | ((TARGET_MODULO) ? OPTION_MASK_MODULO : 0) | ((TARGET_64BIT) ? MASK_64BIT : 0) | ((TARGET_POWERPC64) ? MASK_POWERPC64 : 0) - | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) - | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) + | ((TARGET_CRYPTO) ? OPTION_MASK_CRYPTO : 0) + | ((TARGET_HTM) ? OPTION_MASK_HTM : 0) | ((TARGET_DFP) ? OPTION_MASK_DFP : 0) | ((TARGET_HARD_FLOAT) ? OPTION_MASK_SOFT_FLOAT : 0) | ((TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && !TARGET_IEEEQUAD) ? OPTION_MASK_MULTIPLE : 0) @@ -24044,23 +24044,23 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = }; /* Builtin mask mapping for printing the flags. */ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { - { "altivec", RS6000_BTM_ALTIVEC, false, false }, - { "vsx", RS6000_BTM_VSX, false, false }, - { "fre", RS6000_BTM_FRE, false, false }, + { "altivec", OPTION_MASK_ALTIVEC, false, false }, + { "vsx", OPTION_MASK_VSX, false, false }, + { "fre", OPTION_MASK_POPCNTB, false, false }, { "fres", OPTION_MASK_PPC_GFXOPT, false, false }, { "frsqrte", OPTION_MASK_PPC_GFXOPT, false, false }, { "frsqrtes", OPTION_MASK_POPCNTB, false, false }, { "popcntd", OPTION_MASK_POPCNTD, false, false }, { "cell", OPTION_MASK_FPRND, false, false }, - { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, - { "power9-vector", RS6000_BTM_P9_VECTOR, false, false }, - { "power9-misc", RS6000_BTM_P9_MISC, false, false }, - { "crypto", RS6000_BTM_CRYPTO, false, false }, - { "htm", RS6000_BTM_HTM, false, false }, + { "power8-vector", OPTION_MASK_P8_VECTOR, false, false }, + { "power9-vector", OPTION_MASK_P9_VECTOR, false, false }, + { "power9-misc", OPTION_MASK_P9_MISC, false, false }, + { "crypto", OPTION_MASK_CRYPTO, false, false }, + { "htm", OPTION_MASK_HTM, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, false }, { "hard-float", OPTION_MASK_SOFT_FLOAT, false, false }, { "long-double-128", OPTION_MASK_MULTIPLE, false, false }, { "powerpc64", MASK_POWERPC64, false, false }, { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 384c5f1599a5..72eb473acbc3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -551,15 +551,10 @@ extern int rs6000_vector_align[]; #ifdef TARGET_LITTLE_ENDIAN #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN #endif -#ifdef TARGET_MODULO -#define RS6000_BTM_MODULO OPTION_MASK_MODULO -#endif - - /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a given system. */ @@ -2238,25 +2233,10 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ /* #define MACHINE_no_sched_speculative_load */ /* General flags. */ extern int frame_pointer_needed; - -/* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick a random bit for ldbl128, which isn't in - target_flags. */ -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ -#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ -#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ -#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ -#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ -#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ -#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ -#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ - - enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, RS6000_BTI_opaque_V4SI, RS6000_BTI_V16QI, /* __vector signed char */