[PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support

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* [PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support
@ 2024-06-03 21:53 Patrick O'Neill
  2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
                   ` (2 more replies)
  0 siblings, 3 replies; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-03 21:53 UTC (permalink / raw)
  To: gcc-patches; +Cc: jeffreyalaw, palmer, gnu-toolchain, Patrick O'Neill

The A extension has been split into two parts: Zaamo and Zalrsc.
This patch adds basic support by making the A extension imply Zaamo and
Zalrsc.

Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
Ratification: https://jira.riscv.org/browse/RVS-1995

v2:
Rebased and updated some testcases that rely on the ISA string.

Patrick O'Neill (3):
  RISC-V: Add basic Zaamo and Zalrsc support
  RISC-V: Add Zalrsc and Zaamo testsuite support
  RISC-V: Add Zalrsc amo-op patterns

 gcc/common/config/riscv/riscv-common.cc       |  11 +-
 gcc/config/riscv/arch-canonicalize            |   1 +
 gcc/config/riscv/riscv.opt                    |   6 +-
 gcc/config/riscv/sync.md                      | 152 +++++++++++++++---
 .../riscv/amo-table-a-6-amo-add-1.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-2.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-3.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-4.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-5.c           |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-1.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-2.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-3.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-4.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-5.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-6.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-7.c  |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |   2 +-
 .../riscv/amo-table-ztso-amo-add-1.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-2.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-3.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-4.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-5.c          |   1 +
 .../riscv/amo-table-ztso-compare-exchange-1.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-2.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-3.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-4.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-5.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-6.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-7.c |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |   1 +
 .../riscv/amo-zaamo-preferred-over-zalrsc.c   |  17 ++
 .../gcc.target/riscv/amo-zalrsc-amo-add-1.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-2.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-3.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-4.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-5.c   |  19 +++
 gcc/testsuite/gcc.target/riscv/attribute-15.c |   2 +-
 gcc/testsuite/gcc.target/riscv/attribute-16.c |   2 +-
 gcc/testsuite/gcc.target/riscv/attribute-17.c |   2 +-
 gcc/testsuite/gcc.target/riscv/attribute-18.c |   2 +-
 gcc/testsuite/gcc.target/riscv/pr110696.c     |   2 +-
 .../gcc.target/riscv/rvv/base/pr114352-1.c    |   4 +-
 .../gcc.target/riscv/rvv/base/pr114352-3.c    |   8 +-
 gcc/testsuite/lib/target-supports.exp         | 134 ++++++++++-----
 52 files changed, 395 insertions(+), 94 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c

--
2.34.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
  2024-06-03 21:53 [PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support Patrick O'Neill
@ 2024-06-03 21:53 ` Patrick O'Neill
  2024-06-04  3:00   ` Kito Cheng
  2024-06-07 22:35   ` Jeff Law
  2024-06-03 21:53 ` [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Patrick O'Neill
  2024-06-03 21:53 ` [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns Patrick O'Neill
  2 siblings, 2 replies; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-03 21:53 UTC (permalink / raw)
  To: gcc-patches
  Cc: jeffreyalaw, palmer, gnu-toolchain, Patrick O'Neill, Edwin Lu

The A extension has been split into two parts: Zaamo and Zalrsc.
This patch adds basic support by making the A extension imply Zaamo and
Zalrsc.

Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
Ratification: https://jira.riscv.org/browse/RVS-1995

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
	* config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
	* config/riscv/riscv.opt: Add Zaamo and Zalrsc
	* config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
	TARGET_ZALRSC.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-15.c: Adjust expected arch string.
	* gcc.target/riscv/attribute-16.c: Ditto.
	* gcc.target/riscv/attribute-17.c: Ditto.
	* gcc.target/riscv/attribute-18.c: Ditto.
	* gcc.target/riscv/pr110696.c: Ditto.
	* gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
	* gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/common/config/riscv/riscv-common.cc       | 11 +++++--
 gcc/config/riscv/arch-canonicalize            |  1 +
 gcc/config/riscv/riscv.opt                    |  6 +++-
 gcc/config/riscv/sync.md                      | 30 +++++++++----------
 gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
 gcc/testsuite/gcc.target/riscv/pr110696.c     |  2 +-
 .../gcc.target/riscv/rvv/base/pr114352-1.c    |  4 +--
 .../gcc.target/riscv/rvv/base/pr114352-3.c    |  8 ++---
 11 files changed, 41 insertions(+), 29 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 88204393fde..78dfd6b1470 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"f", "zicsr"},
   {"d", "zicsr"},

+  {"a", "zaamo"},
+  {"a", "zalrsc"},
+
   {"zdinx", "zfinx"},
   {"zfinx", "zicsr"},
   {"zdinx", "zicsr"},
@@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},

   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
   {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},

-  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
+  {"za64rs",  &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
   {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
-  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
+  {"zawrs",   &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
+  {"zaamo",   &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
+  {"zalrsc",  &gcc_options::x_riscv_za_subext, MASK_ZALRSC},

   {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
   {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index 8f7d040cdeb..6c10d1aa81b 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f", "zicsr"],
+  "a" : ["zaamo", "zalrsc"],
   "f" : ["zicsr"],
   "zdinx" : ["zfinx", "zicsr"],
   "zfinx" : ["zicsr"],
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 87f58332016..fa57b4b1090 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -248,7 +248,11 @@ Mask(ZICCRSE)     Var(riscv_zi_subext)
 TargetVariable
 int riscv_za_subext

-Mask(ZAWRS) Var(riscv_za_subext)
+Mask(ZAWRS)  Var(riscv_za_subext)
+
+Mask(ZAAMO)  Var(riscv_za_subext)
+
+Mask(ZALRSC) Var(riscv_za_subext)

 Mask(ZA64RS)  Var(riscv_za_subext)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6f0b5aae08d..c9544176ead 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -93,7 +93,7 @@
 		     (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
 	   (match_operand:SI 2 "const_int_operand")] ;; model
 	 UNSPEC_SYNC_OLD_OP))]
-  "TARGET_ATOMIC"
+  "TARGET_ZAAMO"
   "amo<insn>.<amo>%A2\tzero,%z1,%0"
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])
@@ -107,7 +107,7 @@
 		     (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
 	   (match_operand:SI 3 "const_int_operand")] ;; model
 	 UNSPEC_SYNC_OLD_OP))]
-  "TARGET_ATOMIC"
+  "TARGET_ZAAMO"
   "amo<insn>.<amo>%A3\t%0,%z2,%1"
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])
@@ -125,7 +125,7 @@
     (match_operand:SI 5 "register_operand" "rI")		   ;; not_mask
     (clobber (match_scratch:SI 6 "=&r"))			   ;; tmp_1
     (clobber (match_scratch:SI 7 "=&r"))]			   ;; tmp_2
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
   {
     return "1:\;"
 	   "lr.w%I3\t%0, %1\;"
@@ -144,7 +144,7 @@
    (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand")     ;; mem location
 			 (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
    (match_operand:SI 3 "const_int_operand")]			      ;; model
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
 {
   /* We have no QImode/HImode atomics, so form a mask, then use
      subword_atomic_fetch_strong_nand to implement a LR/SC version of the
@@ -192,7 +192,7 @@
     (match_operand:SI 5 "register_operand" "rI")			  ;; not_mask
     (clobber (match_scratch:SI 6 "=&r"))				  ;; tmp_1
     (clobber (match_scratch:SI 7 "=&r"))]				  ;; tmp_2
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
   {
     return "1:\;"
 	   "lr.w%I3\t%0, %1\;"
@@ -212,7 +212,7 @@
    (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand")	 ;; mem location
 		     (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
    (match_operand:SI 3 "const_int_operand")]			 ;; model
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
 {
   /* We have no QImode/HImode atomics, so form a mask, then use
      subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
@@ -256,7 +256,7 @@
 	  UNSPEC_SYNC_EXCHANGE))
    (set (match_dup 1)
 	(match_operand:GPR 2 "register_operand" "0"))]
-  "TARGET_ATOMIC"
+  "TARGET_ZAAMO"
   "amoswap.<amo>%A3\t%0,%z2,%1"
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])
@@ -266,7 +266,7 @@
    (match_operand:SHORT 1 "memory_operand")   ;; mem location
    (match_operand:SHORT 2 "register_operand") ;; value
    (match_operand:SI 3 "const_int_operand")]  ;; model
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
 {
   rtx old = gen_reg_rtx (SImode);
   rtx mem = operands[1];
@@ -303,7 +303,7 @@
       UNSPEC_SYNC_EXCHANGE_SUBWORD))
     (match_operand:SI 4 "reg_or_0_operand" "rI")	 ;; not_mask
     (clobber (match_scratch:SI 5 "=&r"))]		 ;; tmp_1
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
   {
     return "1:\;"
 	   "lr.w%I3\t%0, %1\;"
@@ -325,7 +325,7 @@
 			      (match_operand:SI 5 "const_int_operand")] ;; mod_f
 	 UNSPEC_COMPARE_AND_SWAP))
    (clobber (match_scratch:GPR 6 "=&r"))]
-  "TARGET_ATOMIC"
+  "TARGET_ZALRSC"
   {
     enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
     enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
@@ -351,7 +351,7 @@
    (match_operand:SI 5 "const_int_operand" "")  ;; is_weak
    (match_operand:SI 6 "const_int_operand" "")  ;; mod_s
    (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
-  "TARGET_ATOMIC"
+  "TARGET_ZALRSC"
 {
   if (word_mode != <MODE>mode && operands[3] != const0_rtx)
     {
@@ -394,7 +394,7 @@
    (match_operand:SI 5 "const_int_operand")   ;; is_weak
    (match_operand:SI 6 "const_int_operand")   ;; mod_s
    (match_operand:SI 7 "const_int_operand")]  ;; mod_f
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
 {
   emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
 						operands[3], operands[4],
@@ -439,7 +439,7 @@
    (match_operand:SI 4 "const_int_operand")   ;; mod_s
    (match_operand:SI 5 "const_int_operand")   ;; mod_f
    (match_scratch:SHORT 6)]
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
 {
   /* We have no QImode/HImode atomics, so form a mask, then use
      subword_atomic_cas_strong<mode> to implement a LR/SC version of the
@@ -497,7 +497,7 @@
 	(match_operand:SI 5 "register_operand" "rI")			   ;; mask
 	(match_operand:SI 6 "register_operand" "rI")			   ;; not_mask
 	(clobber (match_scratch:SI 7 "=&r"))]				   ;; tmp_1
-  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
+  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
   {
     return "1:\;"
 	   "lr.w%I4\t%0, %1\;"
@@ -516,7 +516,7 @@
   [(match_operand:QI 0 "register_operand" "")    ;; bool output
    (match_operand:QI 1 "memory_operand" "+A")    ;; memory
    (match_operand:SI 2 "const_int_operand" "")]  ;; model
-  "TARGET_ATOMIC"
+  "TARGET_ZALRSC"
 {
   /* We have no QImode atomics, so use the address LSBs to form a mask,
      then use an aligned SImode atomic.  */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
index 59efeb6ea45..a2e394b6489 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
index 26f961efb48..d2b18160cb5 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
index 0abff3705d9..fc2f488a3ac 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
index fddbf15fc3e..eefd602103d 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
 int foo() {}
-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
index a630f04e74f..08682a047e0 100644
--- a/gcc/testsuite/gcc.target/riscv/pr110696.c
+++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
@@ -4,4 +4,4 @@ int foo()
 {
 }

-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
index b3f1f20fb79..faeb406498d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count)
     out[i] = a[i] + b[i];
 }

-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
index e7af4223d6a..38815ef5bd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
     out[i] = a[i] + b[i];
 }

-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */
-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
+/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
--
2.34.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
  2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
@ 2024-06-04  3:00   ` Kito Cheng
  2024-06-04 17:30     ` Patrick O'Neill
  2024-06-07 22:35   ` Jeff Law
  1 sibling, 1 reply; 13+ messages in thread
From: Kito Cheng @ 2024-06-04  3:00 UTC (permalink / raw)
  To: Patrick O'Neill
  Cc: gcc-patches, jeffreyalaw, palmer, gnu-toolchain, Edwin Lu

Hi Patrick:

One dumb question around Zaamo and Zalrsc, could we still got correct
atomic semantic with only Zaamo or only Zalrsc? I guess Zalrsc only
probably ok, but how about Zaamo only?

And another question around authorship: I notice you are listed as
co-authored, and signed off by Edwin, but according to the mail (and
the result of git pw patch apply) the main author is you? So I'm just
curious who the main author is? not necessary to list co-authored
again if it's you, and need to update author info if it's Edwin, I
know you guy are in same the company, so that's may not big issue is
not clear, but personally I would like to mention correct authorship
if possible :P

[1] How to update author for single commit:
https://stackoverflow.com/questions/3042437/how-can-i-change-the-commit-author-for-a-single-commit

On Tue, Jun 4, 2024 at 5:54 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> The A extension has been split into two parts: Zaamo and Zalrsc.
> This patch adds basic support by making the A extension imply Zaamo and
> Zalrsc.
>
> Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Ratification: https://jira.riscv.org/browse/RVS-1995
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
>         * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
>         * config/riscv/riscv.opt: Add Zaamo and Zalrsc
>         * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
>         TARGET_ZALRSC.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/attribute-15.c: Adjust expected arch string.
>         * gcc.target/riscv/attribute-16.c: Ditto.
>         * gcc.target/riscv/attribute-17.c: Ditto.
>         * gcc.target/riscv/attribute-18.c: Ditto.
>         * gcc.target/riscv/pr110696.c: Ditto.
>         * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
>         * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> Co-authored-by: Patrick O'Neill <patrick@rivosinc.com>
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 11 +++++--
>  gcc/config/riscv/arch-canonicalize            |  1 +
>  gcc/config/riscv/riscv.opt                    |  6 +++-
>  gcc/config/riscv/sync.md                      | 30 +++++++++----------
>  gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/pr110696.c     |  2 +-
>  .../gcc.target/riscv/rvv/base/pr114352-1.c    |  4 +--
>  .../gcc.target/riscv/rvv/base/pr114352-3.c    |  8 ++---
>  11 files changed, 41 insertions(+), 29 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 88204393fde..78dfd6b1470 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
>    {"f", "zicsr"},
>    {"d", "zicsr"},
>
> +  {"a", "zaamo"},
> +  {"a", "zalrsc"},
> +
>    {"zdinx", "zfinx"},
>    {"zfinx", "zicsr"},
>    {"zdinx", "zicsr"},
> @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
>    {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>    {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>
> -  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za64rs",  &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
>    {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
> -  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zawrs",   &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zaamo",   &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
> +  {"zalrsc",  &gcc_options::x_riscv_za_subext, MASK_ZALRSC},
>
>    {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
>    {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
> index 8f7d040cdeb..6c10d1aa81b 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
>  #
>  IMPLIED_EXT = {
>    "d" : ["f", "zicsr"],
> +  "a" : ["zaamo", "zalrsc"],
>    "f" : ["zicsr"],
>    "zdinx" : ["zfinx", "zicsr"],
>    "zfinx" : ["zicsr"],
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 87f58332016..fa57b4b1090 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -248,7 +248,11 @@ Mask(ZICCRSE)     Var(riscv_zi_subext)
>  TargetVariable
>  int riscv_za_subext
>
> -Mask(ZAWRS) Var(riscv_za_subext)
> +Mask(ZAWRS)  Var(riscv_za_subext)
> +
> +Mask(ZAAMO)  Var(riscv_za_subext)
> +
> +Mask(ZALRSC) Var(riscv_za_subext)
>
>  Mask(ZA64RS)  Var(riscv_za_subext)
>
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index 6f0b5aae08d..c9544176ead 100644
> --- a/gcc/config/riscv/sync.md
> +++ b/gcc/config/riscv/sync.md
> @@ -93,7 +93,7 @@
>                      (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
>            (match_operand:SI 2 "const_int_operand")] ;; model
>          UNSPEC_SYNC_OLD_OP))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amo<insn>.<amo>%A2\tzero,%z1,%0"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -107,7 +107,7 @@
>                      (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
>            (match_operand:SI 3 "const_int_operand")] ;; model
>          UNSPEC_SYNC_OLD_OP))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amo<insn>.<amo>%A3\t%0,%z2,%1"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -125,7 +125,7 @@
>      (match_operand:SI 5 "register_operand" "rI")                  ;; not_mask
>      (clobber (match_scratch:SI 6 "=&r"))                          ;; tmp_1
>      (clobber (match_scratch:SI 7 "=&r"))]                         ;; tmp_2
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -144,7 +144,7 @@
>     (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand")     ;; mem location
>                          (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
>     (match_operand:SI 3 "const_int_operand")]                         ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_fetch_strong_nand to implement a LR/SC version of the
> @@ -192,7 +192,7 @@
>      (match_operand:SI 5 "register_operand" "rI")                         ;; not_mask
>      (clobber (match_scratch:SI 6 "=&r"))                                 ;; tmp_1
>      (clobber (match_scratch:SI 7 "=&r"))]                                ;; tmp_2
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -212,7 +212,7 @@
>     (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand")   ;; mem location
>                      (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
>     (match_operand:SI 3 "const_int_operand")]                    ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
> @@ -256,7 +256,7 @@
>           UNSPEC_SYNC_EXCHANGE))
>     (set (match_dup 1)
>         (match_operand:GPR 2 "register_operand" "0"))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amoswap.<amo>%A3\t%0,%z2,%1"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -266,7 +266,7 @@
>     (match_operand:SHORT 1 "memory_operand")   ;; mem location
>     (match_operand:SHORT 2 "register_operand") ;; value
>     (match_operand:SI 3 "const_int_operand")]  ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    rtx old = gen_reg_rtx (SImode);
>    rtx mem = operands[1];
> @@ -303,7 +303,7 @@
>        UNSPEC_SYNC_EXCHANGE_SUBWORD))
>      (match_operand:SI 4 "reg_or_0_operand" "rI")        ;; not_mask
>      (clobber (match_scratch:SI 5 "=&r"))]               ;; tmp_1
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -325,7 +325,7 @@
>                               (match_operand:SI 5 "const_int_operand")] ;; mod_f
>          UNSPEC_COMPARE_AND_SWAP))
>     (clobber (match_scratch:GPR 6 "=&r"))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>    {
>      enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
>      enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
> @@ -351,7 +351,7 @@
>     (match_operand:SI 5 "const_int_operand" "")  ;; is_weak
>     (match_operand:SI 6 "const_int_operand" "")  ;; mod_s
>     (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>  {
>    if (word_mode != <MODE>mode && operands[3] != const0_rtx)
>      {
> @@ -394,7 +394,7 @@
>     (match_operand:SI 5 "const_int_operand")   ;; is_weak
>     (match_operand:SI 6 "const_int_operand")   ;; mod_s
>     (match_operand:SI 7 "const_int_operand")]  ;; mod_f
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
>                                                 operands[3], operands[4],
> @@ -439,7 +439,7 @@
>     (match_operand:SI 4 "const_int_operand")   ;; mod_s
>     (match_operand:SI 5 "const_int_operand")   ;; mod_f
>     (match_scratch:SHORT 6)]
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_cas_strong<mode> to implement a LR/SC version of the
> @@ -497,7 +497,7 @@
>         (match_operand:SI 5 "register_operand" "rI")                       ;; mask
>         (match_operand:SI 6 "register_operand" "rI")                       ;; not_mask
>         (clobber (match_scratch:SI 7 "=&r"))]                              ;; tmp_1
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I4\t%0, %1\;"
> @@ -516,7 +516,7 @@
>    [(match_operand:QI 0 "register_operand" "")    ;; bool output
>     (match_operand:QI 1 "memory_operand" "+A")    ;; memory
>     (match_operand:SI 2 "const_int_operand" "")]  ;; model
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>  {
>    /* We have no QImode atomics, so use the address LSBs to form a mask,
>       then use an aligned SImode atomic.  */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> index 59efeb6ea45..a2e394b6489 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> index 26f961efb48..d2b18160cb5 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> index 0abff3705d9..fc2f488a3ac 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> index fddbf15fc3e..eefd602103d 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> @@ -1,4 +1,4 @@
>  /* { dg-do compile } */
>  /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
>  int foo() {}
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
> index a630f04e74f..08682a047e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -4,4 +4,4 @@ int foo()
>  {
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> index b3f1f20fb79..faeb406498d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count)
>      out[i] = a[i] + b[i];
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> index e7af4223d6a..38815ef5bd0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
>      out[i] = a[i] + b[i];
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
  2024-06-04  3:00   ` Kito Cheng
@ 2024-06-04 17:30     ` Patrick O'Neill
  2024-06-04 21:27       ` Andrew Waterman
  0 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-04 17:30 UTC (permalink / raw)
  To: Kito Cheng; +Cc: gcc-patches, jeffreyalaw, palmer, gnu-toolchain, Edwin Lu

[-- Attachment #1: Type: text/plain, Size: 18873 bytes --]

On 6/3/24 20:00, Kito Cheng wrote:

> Hi Patrick:
>
> One dumb question around Zaamo and Zalrsc, could we still got correct
> atomic semantic with only Zaamo or only Zalrsc? I guess Zalrsc only
> probably ok, but how about Zaamo only?

This is a very valid question - AFAIK Zalrsc is always correct and
Zaamo is _not_ always correct.

We use the mappings present in the PSABI doc when directly emitting
insns.

LR/SC sequences can approximate atomic insns with a retry loop so it
will emit valid asm for any 'a' extension usage (patch 3/3 adds this
support).

Zaamo cannot approximate LR/SC sequences so GCC emit a libatomic call
if your code requires an LR/SC.This _is_ invalid behavior and is discussed here: 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005 TLDR: Zaamo can only 
support amo ops and will emit calls for LR/SC ops which is invalid 
behavior when mixed with atomic loads/stores/amo ops (currently 
observable on trunk with non-atomic targets emitting fenced loads/stores 
mixed with libatomic calls).

> And another question around authorship: I notice you are listed as
> co-authored, and signed off by Edwin, but according to the mail (and
> the result of git pw patch apply) the main author is you? So I'm just
> curious who the main author is? not necessary to list co-authored
> again if it's you, and need to update author info if it's Edwin, I
> know you guy are in same the company, so that's may not big issue is
> not clear, but personally I would like to mention correct authorship
> if possible :P

Edwin wrote the initial 1/3 patch and I did edits on top of that.
Authorship got clobbered when I was rebasing. If this revision
gets approved I'll fix it before merging. Thanks for catching this!

Thanks!
Patrick

>
> [1] How to update author for single commit:
> https://stackoverflow.com/questions/3042437/how-can-i-change-the-commit-author-for-a-single-commit
>
> On Tue, Jun 4, 2024 at 5:54 AM Patrick O'Neill<patrick@rivosinc.com>  wrote:
>> The A extension has been split into two parts: Zaamo and Zalrsc.
>> This patch adds basic support by making the A extension imply Zaamo and
>> Zalrsc.
>>
>> Zaamo/Zalrsc spec:https://github.com/riscv/riscv-zaamo-zalrsc/tags
>> Ratification:https://jira.riscv.org/browse/RVS-1995
>>
>> gcc/ChangeLog:
>>
>>          * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
>>          * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
>>          * config/riscv/riscv.opt: Add Zaamo and Zalrsc
>>          * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
>>          TARGET_ZALRSC.
>>
>> gcc/testsuite/ChangeLog:
>>
>>          * gcc.target/riscv/attribute-15.c: Adjust expected arch string.
>>          * gcc.target/riscv/attribute-16.c: Ditto.
>>          * gcc.target/riscv/attribute-17.c: Ditto.
>>          * gcc.target/riscv/attribute-18.c: Ditto.
>>          * gcc.target/riscv/pr110696.c: Ditto.
>>          * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
>>          * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
>>
>> Signed-off-by: Edwin Lu<ewlu@rivosinc.com>
>> Co-authored-by: Patrick O'Neill<patrick@rivosinc.com>
>> ---
>>   gcc/common/config/riscv/riscv-common.cc       | 11 +++++--
>>   gcc/config/riscv/arch-canonicalize            |  1 +
>>   gcc/config/riscv/riscv.opt                    |  6 +++-
>>   gcc/config/riscv/sync.md                      | 30 +++++++++----------
>>   gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
>>   gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
>>   gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
>>   gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
>>   gcc/testsuite/gcc.target/riscv/pr110696.c     |  2 +-
>>   .../gcc.target/riscv/rvv/base/pr114352-1.c    |  4 +--
>>   .../gcc.target/riscv/rvv/base/pr114352-3.c    |  8 ++---
>>   11 files changed, 41 insertions(+), 29 deletions(-)
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
>> index 88204393fde..78dfd6b1470 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>     {"f", "zicsr"},
>>     {"d", "zicsr"},
>>
>> +  {"a", "zaamo"},
>> +  {"a", "zalrsc"},
>> +
>>     {"zdinx", "zfinx"},
>>     {"zfinx", "zicsr"},
>>     {"zdinx", "zicsr"},
>> @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>>     {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
>>     {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>>     {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
>> +  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
>> +  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
>>
>>     {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>>     {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
>> @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>>     {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>>     {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>>
>> -  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
>> +  {"za64rs",  &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
>>     {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
>> -  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
>> +  {"zawrs",   &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
>> +  {"zaamo",   &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
>> +  {"zalrsc",  &gcc_options::x_riscv_za_subext, MASK_ZALRSC},
>>
>>     {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
>>     {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
>> diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
>> index 8f7d040cdeb..6c10d1aa81b 100755
>> --- a/gcc/config/riscv/arch-canonicalize
>> +++ b/gcc/config/riscv/arch-canonicalize
>> @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
>>   #
>>   IMPLIED_EXT = {
>>     "d" : ["f", "zicsr"],
>> +  "a" : ["zaamo", "zalrsc"],
>>     "f" : ["zicsr"],
>>     "zdinx" : ["zfinx", "zicsr"],
>>     "zfinx" : ["zicsr"],
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index 87f58332016..fa57b4b1090 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/riscv/riscv.opt
>> @@ -248,7 +248,11 @@ Mask(ZICCRSE)     Var(riscv_zi_subext)
>>   TargetVariable
>>   int riscv_za_subext
>>
>> -Mask(ZAWRS) Var(riscv_za_subext)
>> +Mask(ZAWRS)  Var(riscv_za_subext)
>> +
>> +Mask(ZAAMO)  Var(riscv_za_subext)
>> +
>> +Mask(ZALRSC) Var(riscv_za_subext)
>>
>>   Mask(ZA64RS)  Var(riscv_za_subext)
>>
>> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
>> index 6f0b5aae08d..c9544176ead 100644
>> --- a/gcc/config/riscv/sync.md
>> +++ b/gcc/config/riscv/sync.md
>> @@ -93,7 +93,7 @@
>>                       (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
>>             (match_operand:SI 2 "const_int_operand")] ;; model
>>           UNSPEC_SYNC_OLD_OP))]
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZAAMO"
>>     "amo<insn>.<amo>%A2\tzero,%z1,%0"
>>     [(set_attr "type" "atomic")
>>      (set (attr "length") (const_int 4))])
>> @@ -107,7 +107,7 @@
>>                       (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
>>             (match_operand:SI 3 "const_int_operand")] ;; model
>>           UNSPEC_SYNC_OLD_OP))]
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZAAMO"
>>     "amo<insn>.<amo>%A3\t%0,%z2,%1"
>>     [(set_attr "type" "atomic")
>>      (set (attr "length") (const_int 4))])
>> @@ -125,7 +125,7 @@
>>       (match_operand:SI 5 "register_operand" "rI")                  ;; not_mask
>>       (clobber (match_scratch:SI 6 "=&r"))                          ;; tmp_1
>>       (clobber (match_scratch:SI 7 "=&r"))]                         ;; tmp_2
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>     {
>>       return "1:\;"
>>             "lr.w%I3\t%0, %1\;"
>> @@ -144,7 +144,7 @@
>>      (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand")     ;; mem location
>>                           (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
>>      (match_operand:SI 3 "const_int_operand")]                         ;; model
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>   {
>>     /* We have no QImode/HImode atomics, so form a mask, then use
>>        subword_atomic_fetch_strong_nand to implement a LR/SC version of the
>> @@ -192,7 +192,7 @@
>>       (match_operand:SI 5 "register_operand" "rI")                         ;; not_mask
>>       (clobber (match_scratch:SI 6 "=&r"))                                 ;; tmp_1
>>       (clobber (match_scratch:SI 7 "=&r"))]                                ;; tmp_2
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>     {
>>       return "1:\;"
>>             "lr.w%I3\t%0, %1\;"
>> @@ -212,7 +212,7 @@
>>      (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand")   ;; mem location
>>                       (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
>>      (match_operand:SI 3 "const_int_operand")]                    ;; model
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>   {
>>     /* We have no QImode/HImode atomics, so form a mask, then use
>>        subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
>> @@ -256,7 +256,7 @@
>>            UNSPEC_SYNC_EXCHANGE))
>>      (set (match_dup 1)
>>          (match_operand:GPR 2 "register_operand" "0"))]
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZAAMO"
>>     "amoswap.<amo>%A3\t%0,%z2,%1"
>>     [(set_attr "type" "atomic")
>>      (set (attr "length") (const_int 4))])
>> @@ -266,7 +266,7 @@
>>      (match_operand:SHORT 1 "memory_operand")   ;; mem location
>>      (match_operand:SHORT 2 "register_operand") ;; value
>>      (match_operand:SI 3 "const_int_operand")]  ;; model
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>   {
>>     rtx old = gen_reg_rtx (SImode);
>>     rtx mem = operands[1];
>> @@ -303,7 +303,7 @@
>>         UNSPEC_SYNC_EXCHANGE_SUBWORD))
>>       (match_operand:SI 4 "reg_or_0_operand" "rI")        ;; not_mask
>>       (clobber (match_scratch:SI 5 "=&r"))]               ;; tmp_1
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>     {
>>       return "1:\;"
>>             "lr.w%I3\t%0, %1\;"
>> @@ -325,7 +325,7 @@
>>                                (match_operand:SI 5 "const_int_operand")] ;; mod_f
>>           UNSPEC_COMPARE_AND_SWAP))
>>      (clobber (match_scratch:GPR 6 "=&r"))]
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZALRSC"
>>     {
>>       enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
>>       enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
>> @@ -351,7 +351,7 @@
>>      (match_operand:SI 5 "const_int_operand" "")  ;; is_weak
>>      (match_operand:SI 6 "const_int_operand" "")  ;; mod_s
>>      (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZALRSC"
>>   {
>>     if (word_mode != <MODE>mode && operands[3] != const0_rtx)
>>       {
>> @@ -394,7 +394,7 @@
>>      (match_operand:SI 5 "const_int_operand")   ;; is_weak
>>      (match_operand:SI 6 "const_int_operand")   ;; mod_s
>>      (match_operand:SI 7 "const_int_operand")]  ;; mod_f
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>   {
>>     emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
>>                                                  operands[3], operands[4],
>> @@ -439,7 +439,7 @@
>>      (match_operand:SI 4 "const_int_operand")   ;; mod_s
>>      (match_operand:SI 5 "const_int_operand")   ;; mod_f
>>      (match_scratch:SHORT 6)]
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>   {
>>     /* We have no QImode/HImode atomics, so form a mask, then use
>>        subword_atomic_cas_strong<mode> to implement a LR/SC version of the
>> @@ -497,7 +497,7 @@
>>          (match_operand:SI 5 "register_operand" "rI")                       ;; mask
>>          (match_operand:SI 6 "register_operand" "rI")                       ;; not_mask
>>          (clobber (match_scratch:SI 7 "=&r"))]                              ;; tmp_1
>> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
>> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>>     {
>>       return "1:\;"
>>             "lr.w%I4\t%0, %1\;"
>> @@ -516,7 +516,7 @@
>>     [(match_operand:QI 0 "register_operand" "")    ;; bool output
>>      (match_operand:QI 1 "memory_operand" "+A")    ;; memory
>>      (match_operand:SI 2 "const_int_operand" "")]  ;; model
>> -  "TARGET_ATOMIC"
>> +  "TARGET_ZALRSC"
>>   {
>>     /* We have no QImode atomics, so use the address LSBs to form a mask,
>>        then use an aligned SImode atomic.  */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
>> index 59efeb6ea45..a2e394b6489 100644
>> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
>> @@ -3,4 +3,4 @@
>>   int foo()
>>   {
>>   }
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
>> index 26f961efb48..d2b18160cb5 100644
>> --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
>> @@ -3,4 +3,4 @@
>>   int foo()
>>   {
>>   }
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
>> index 0abff3705d9..fc2f488a3ac 100644
>> --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
>> @@ -3,4 +3,4 @@
>>   int foo()
>>   {
>>   }
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
>> index fddbf15fc3e..eefd602103d 100644
>> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
>> @@ -1,4 +1,4 @@
>>   /* { dg-do compile } */
>>   /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
>>   int foo() {}
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
>> index a630f04e74f..08682a047e0 100644
>> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c
>> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
>> @@ -4,4 +4,4 @@ int foo()
>>   {
>>   }
>>
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
>> index b3f1f20fb79..faeb406498d 100644
>> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
>> @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count)
>>       out[i] = a[i] + b[i];
>>   }
>>
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
>> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
>> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
>> index e7af4223d6a..38815ef5bd0 100644
>> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
>> @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
>>       out[i] = a[i] + b[i];
>>   }
>>
>> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
>> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
>> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */
>> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
>> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
>> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
>> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
>> --
>> 2.34.1
>>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
  2024-06-04 17:30     ` Patrick O'Neill
@ 2024-06-04 21:27       ` Andrew Waterman
  0 siblings, 0 replies; 13+ messages in thread
From: Andrew Waterman @ 2024-06-04 21:27 UTC (permalink / raw)
  To: Patrick O'Neill
  Cc: Kito Cheng, gcc-patches, jeffreyalaw, palmer, gnu-toolchain, Edwin Lu

On Tue, Jun 4, 2024 at 10:31 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> On 6/3/24 20:00, Kito Cheng wrote:
>
> Hi Patrick:
>
> One dumb question around Zaamo and Zalrsc, could we still got correct
> atomic semantic with only Zaamo or only Zalrsc? I guess Zalrsc only
> probably ok, but how about Zaamo only?
>
> This is a very valid question - AFAIK Zalrsc is always correct and
> Zaamo is _not_ always correct.
>
> We use the mappings present in the PSABI doc when directly emitting
> insns.
>
> LR/SC sequences can approximate atomic insns with a retry loop so it
> will emit valid asm for any 'a' extension usage (patch 3/3 adds this
> support).
>
> Zaamo cannot approximate LR/SC sequences so GCC emit a libatomic call
> if your code requires an LR/SC. This _is_ invalid behavior and is
> discussed here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005

Note also there's an old proof that the Zaamo instructions are
insufficient to emulate CAS.  Since LR/SC _is_ sufficient to emulate
CAS, it follows logically that Zaamo is insufficient to emulate LR/SC.
https://cs.brown.edu/~mph/Herlihy91/p124-herlihy.pdf

>
> TLDR: Zaamo can only support amo ops and will emit calls for LR/SC
> ops which is invalid behavior when mixed with atomic
> loads/stores/amo ops (currently observable on trunk with non-atomic
> targets emitting fenced loads/stores mixed with libatomic calls).
>
> And another question around authorship: I notice you are listed as
> co-authored, and signed off by Edwin, but according to the mail (and
> the result of git pw patch apply) the main author is you? So I'm just
> curious who the main author is? not necessary to list co-authored
> again if it's you, and need to update author info if it's Edwin, I
> know you guy are in same the company, so that's may not big issue is
> not clear, but personally I would like to mention correct authorship
> if possible :P
>
> Edwin wrote the initial 1/3 patch and I did edits on top of that.
> Authorship got clobbered when I was rebasing. If this revision
> gets approved I'll fix it before merging. Thanks for catching this!
>
> Thanks!
> Patrick
>
> [1] How to update author for single commit:
> https://stackoverflow.com/questions/3042437/how-can-i-change-the-commit-author-for-a-single-commit
>
> On Tue, Jun 4, 2024 at 5:54 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> The A extension has been split into two parts: Zaamo and Zalrsc.
> This patch adds basic support by making the A extension imply Zaamo and
> Zalrsc.
>
> Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Ratification: https://jira.riscv.org/browse/RVS-1995
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
>         * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
>         * config/riscv/riscv.opt: Add Zaamo and Zalrsc
>         * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
>         TARGET_ZALRSC.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/attribute-15.c: Adjust expected arch string.
>         * gcc.target/riscv/attribute-16.c: Ditto.
>         * gcc.target/riscv/attribute-17.c: Ditto.
>         * gcc.target/riscv/attribute-18.c: Ditto.
>         * gcc.target/riscv/pr110696.c: Ditto.
>         * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
>         * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> Co-authored-by: Patrick O'Neill <patrick@rivosinc.com>
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 11 +++++--
>  gcc/config/riscv/arch-canonicalize            |  1 +
>  gcc/config/riscv/riscv.opt                    |  6 +++-
>  gcc/config/riscv/sync.md                      | 30 +++++++++----------
>  gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/pr110696.c     |  2 +-
>  .../gcc.target/riscv/rvv/base/pr114352-1.c    |  4 +--
>  .../gcc.target/riscv/rvv/base/pr114352-3.c    |  8 ++---
>  11 files changed, 41 insertions(+), 29 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 88204393fde..78dfd6b1470 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
>    {"f", "zicsr"},
>    {"d", "zicsr"},
>
> +  {"a", "zaamo"},
> +  {"a", "zalrsc"},
> +
>    {"zdinx", "zfinx"},
>    {"zfinx", "zicsr"},
>    {"zdinx", "zicsr"},
> @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
>    {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>    {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>
> -  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za64rs",  &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
>    {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
> -  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zawrs",   &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zaamo",   &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
> +  {"zalrsc",  &gcc_options::x_riscv_za_subext, MASK_ZALRSC},
>
>    {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
>    {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
> index 8f7d040cdeb..6c10d1aa81b 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
>  #
>  IMPLIED_EXT = {
>    "d" : ["f", "zicsr"],
> +  "a" : ["zaamo", "zalrsc"],
>    "f" : ["zicsr"],
>    "zdinx" : ["zfinx", "zicsr"],
>    "zfinx" : ["zicsr"],
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 87f58332016..fa57b4b1090 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -248,7 +248,11 @@ Mask(ZICCRSE)     Var(riscv_zi_subext)
>  TargetVariable
>  int riscv_za_subext
>
> -Mask(ZAWRS) Var(riscv_za_subext)
> +Mask(ZAWRS)  Var(riscv_za_subext)
> +
> +Mask(ZAAMO)  Var(riscv_za_subext)
> +
> +Mask(ZALRSC) Var(riscv_za_subext)
>
>  Mask(ZA64RS)  Var(riscv_za_subext)
>
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index 6f0b5aae08d..c9544176ead 100644
> --- a/gcc/config/riscv/sync.md
> +++ b/gcc/config/riscv/sync.md
> @@ -93,7 +93,7 @@
>                      (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
>            (match_operand:SI 2 "const_int_operand")] ;; model
>          UNSPEC_SYNC_OLD_OP))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amo<insn>.<amo>%A2\tzero,%z1,%0"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -107,7 +107,7 @@
>                      (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
>            (match_operand:SI 3 "const_int_operand")] ;; model
>          UNSPEC_SYNC_OLD_OP))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amo<insn>.<amo>%A3\t%0,%z2,%1"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -125,7 +125,7 @@
>      (match_operand:SI 5 "register_operand" "rI")                  ;; not_mask
>      (clobber (match_scratch:SI 6 "=&r"))                          ;; tmp_1
>      (clobber (match_scratch:SI 7 "=&r"))]                         ;; tmp_2
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -144,7 +144,7 @@
>     (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand")     ;; mem location
>                          (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
>     (match_operand:SI 3 "const_int_operand")]                         ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_fetch_strong_nand to implement a LR/SC version of the
> @@ -192,7 +192,7 @@
>      (match_operand:SI 5 "register_operand" "rI")                         ;; not_mask
>      (clobber (match_scratch:SI 6 "=&r"))                                 ;; tmp_1
>      (clobber (match_scratch:SI 7 "=&r"))]                                ;; tmp_2
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -212,7 +212,7 @@
>     (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand")   ;; mem location
>                      (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
>     (match_operand:SI 3 "const_int_operand")]                    ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
> @@ -256,7 +256,7 @@
>           UNSPEC_SYNC_EXCHANGE))
>     (set (match_dup 1)
>         (match_operand:GPR 2 "register_operand" "0"))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZAAMO"
>    "amoswap.<amo>%A3\t%0,%z2,%1"
>    [(set_attr "type" "atomic")
>     (set (attr "length") (const_int 4))])
> @@ -266,7 +266,7 @@
>     (match_operand:SHORT 1 "memory_operand")   ;; mem location
>     (match_operand:SHORT 2 "register_operand") ;; value
>     (match_operand:SI 3 "const_int_operand")]  ;; model
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    rtx old = gen_reg_rtx (SImode);
>    rtx mem = operands[1];
> @@ -303,7 +303,7 @@
>        UNSPEC_SYNC_EXCHANGE_SUBWORD))
>      (match_operand:SI 4 "reg_or_0_operand" "rI")        ;; not_mask
>      (clobber (match_scratch:SI 5 "=&r"))]               ;; tmp_1
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I3\t%0, %1\;"
> @@ -325,7 +325,7 @@
>                               (match_operand:SI 5 "const_int_operand")] ;; mod_f
>          UNSPEC_COMPARE_AND_SWAP))
>     (clobber (match_scratch:GPR 6 "=&r"))]
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>    {
>      enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
>      enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
> @@ -351,7 +351,7 @@
>     (match_operand:SI 5 "const_int_operand" "")  ;; is_weak
>     (match_operand:SI 6 "const_int_operand" "")  ;; mod_s
>     (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>  {
>    if (word_mode != <MODE>mode && operands[3] != const0_rtx)
>      {
> @@ -394,7 +394,7 @@
>     (match_operand:SI 5 "const_int_operand")   ;; is_weak
>     (match_operand:SI 6 "const_int_operand")   ;; mod_s
>     (match_operand:SI 7 "const_int_operand")]  ;; mod_f
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
>                                                 operands[3], operands[4],
> @@ -439,7 +439,7 @@
>     (match_operand:SI 4 "const_int_operand")   ;; mod_s
>     (match_operand:SI 5 "const_int_operand")   ;; mod_f
>     (match_scratch:SHORT 6)]
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>  {
>    /* We have no QImode/HImode atomics, so form a mask, then use
>       subword_atomic_cas_strong<mode> to implement a LR/SC version of the
> @@ -497,7 +497,7 @@
>         (match_operand:SI 5 "register_operand" "rI")                       ;; mask
>         (match_operand:SI 6 "register_operand" "rI")                       ;; not_mask
>         (clobber (match_scratch:SI 7 "=&r"))]                              ;; tmp_1
> -  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> +  "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
>    {
>      return "1:\;"
>            "lr.w%I4\t%0, %1\;"
> @@ -516,7 +516,7 @@
>    [(match_operand:QI 0 "register_operand" "")    ;; bool output
>     (match_operand:QI 1 "memory_operand" "+A")    ;; memory
>     (match_operand:SI 2 "const_int_operand" "")]  ;; model
> -  "TARGET_ATOMIC"
> +  "TARGET_ZALRSC"
>  {
>    /* We have no QImode atomics, so use the address LSBs to form a mask,
>       then use an aligned SImode atomic.  */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> index 59efeb6ea45..a2e394b6489 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> index 26f961efb48..d2b18160cb5 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> index 0abff3705d9..fc2f488a3ac 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> index fddbf15fc3e..eefd602103d 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> @@ -1,4 +1,4 @@
>  /* { dg-do compile } */
>  /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
>  int foo() {}
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
> index a630f04e74f..08682a047e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -4,4 +4,4 @@ int foo()
>  {
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> index b3f1f20fb79..faeb406498d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count)
>      out[i] = a[i] + b[i];
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> index e7af4223d6a..38815ef5bd0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
>      out[i] = a[i] + b[i];
>  }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
  2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
  2024-06-04  3:00   ` Kito Cheng
@ 2024-06-07 22:35   ` Jeff Law
  1 sibling, 0 replies; 13+ messages in thread
From: Jeff Law @ 2024-06-07 22:35 UTC (permalink / raw)
  To: Patrick O'Neill, gcc-patches; +Cc: palmer, gnu-toolchain, Edwin Lu



On 6/3/24 3:53 PM, Patrick O'Neill wrote:
> The A extension has been split into two parts: Zaamo and Zalrsc.
> This patch adds basic support by making the A extension imply Zaamo and
> Zalrsc.
> 
> Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Ratification: https://jira.riscv.org/browse/RVS-1995
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
> 	* config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
> 	* config/riscv/riscv.opt: Add Zaamo and Zalrsc
> 	* config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
> 	TARGET_ZALRSC.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/attribute-15.c: Adjust expected arch string.
> 	* gcc.target/riscv/attribute-16.c: Ditto.
> 	* gcc.target/riscv/attribute-17.c: Ditto.
> 	* gcc.target/riscv/attribute-18.c: Ditto.
> 	* gcc.target/riscv/pr110696.c: Ditto.
> 	* gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
> 	* gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
OK
jeff


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
  2024-06-03 21:53 [PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support Patrick O'Neill
  2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
@ 2024-06-03 21:53 ` Patrick O'Neill
  2024-06-07 23:04   ` Jeff Law
  2024-06-03 21:53 ` [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns Patrick O'Neill
  2 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-03 21:53 UTC (permalink / raw)
  To: gcc-patches; +Cc: jeffreyalaw, palmer, gnu-toolchain, Patrick O'Neill

Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A.
	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather
	than A.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather
	than A.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
	* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather
	than A.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
	* lib/target-supports.exp: Add testsuite infrastructure support for
	Zaamo and Zalrsc.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 .../riscv/amo-table-a-6-amo-add-1.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-2.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-3.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-4.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-5.c           |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-1.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-2.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-3.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-4.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-5.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-6.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-7.c  |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |   2 +-
 .../riscv/amo-table-ztso-amo-add-1.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-2.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-3.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-4.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-5.c          |   1 +
 .../riscv/amo-table-ztso-compare-exchange-1.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-2.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-3.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-4.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-5.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-6.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-7.c |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |   1 +
 gcc/testsuite/lib/target-supports.exp         | 134 ++++++++++++------
 35 files changed, 124 insertions(+), 61 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
index 8ab1a02b40c..9c2ba39789a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
index a5a841abdcd..b7682a5bab4 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
index f523821b658..c8776872d91 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
index f1561b52c89..b37c4c3f242 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
index 81f876ee625..8d45ca7a347 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
index dc445f0316a..4917cd6bd2b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
index 7e8ab7bb5ef..121936507e3 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
index 4cb6c422213..649c7d2b1fe 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
index da81c34b92c..5f7fdeb1b21 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
index bb16ccc754c..f4bd7d6d842 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
index 0f3f0b49d95..154764425ae 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* Mixed mappings need to be unioned.  */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
index d51de56cc78..16712540919 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
index ca8aa715bed..4174fdee352 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
index e64759a54ae..4c06c90b558 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
index 9d3f69264fa..7e791c901b6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
index ba32ed59c2f..76f3be27110 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
index f9be8c5e628..8dbfa9c4fc8 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index a9edc33ff39..6def4a46712 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index ad843402bcc..88850d7dc07 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
index bdae5bb83a6..400c95d3e53 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
index 815a72f1e56..cec3e5d1962 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
index eda6f01096e..7bbe30b0d66 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
index b6315c45e85..8f44ffd3eef 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
index e487184f6cf..08942d777e6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
index e9c925f0923..47bbab11185 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
index 6b454559633..197dc9b3fd5 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
index 02c9f0ada77..8bf094286b3 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
index 75abd5d3dfb..4fe739197b6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
index 33928c0eac4..9107b5832d5 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
index 2a40d6b1376..5135e2ef25d 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
index c79380f2611..4a99833c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
index d1a94eccfa8..c5a38418ca7 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
index 3d65bc2f64a..64fe80e767a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
index 10354387a13..ac5b5d32c47 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 836545b4e11..48d8375a07a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -28,7 +28,7 @@
 # If ARGS is not empty, its first element is a string that
 # should be added to the command line.
 #
-# Assume by default that CONTENTS is C code.
+# Assume by default that CONTENTS is C code.
 # Otherwise, code should contain:
 # "/* Assembly" for assembly code,
 # "// C++" for c++,
@@ -39,12 +39,12 @@
 # "// Go" for Go
 # "// Rust" for Rust
 # and "(* Modula-2" for Modula-2
-# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
+# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
 # allow for ObjC/ObjC++ specific flags.

 proc check_compile {basename type contents args} {
     global tool
-    verbose "check_compile tool: $tool for $basename"
+    verbose "check_compile tool: $tool for $basename"

     # Save additional_sources to avoid compiling testsuite's sources
     # against check_compile's source.
@@ -100,7 +100,7 @@ proc check_compile {basename type contents args} {
     global compiler_flags
     set save_compiler_flags $compiler_flags
     set lines [${tool}_target_compile $src $output $compile_type "$options"]
-    set compiler_flags $save_compiler_flags
+    set compiler_flags $save_compiler_flags
     file delete $src

     set scan_output $output
@@ -569,7 +569,7 @@ proc check_ifunc_available { } {
 	#endif
 	extern void f_ ();
  	typedef void F (void);
-	F* g (void) { return &f_; }
+	F* g (void) { return &f_; }
 	void f () __attribute__ ((ifunc ("g")));
 	#ifdef __cplusplus
 	}
@@ -631,7 +631,7 @@ proc check_dot_available { } {

 # Return 1 if according to target_info struct and explicit target list
 # target is supposed to support trampolines.
-
+
 proc check_effective_target_trampolines { } {
     if [target_info exists gcc,no_trampolines] {
       return 0
@@ -695,7 +695,7 @@ proc check_effective_target_signal { } {
 # Return 1 if according to target_info struct and explicit target list
 # target disables -fdelete-null-pointer-checks.  Targets should return 0
 # if they simply default to -fno-delete-null-pointer-checks but obey
-# -fdelete-null-pointer-checks when passed explicitly (and tests that
+# -fdelete-null-pointer-checks when passed explicitly (and tests that
 # depend on this option should do that).

 proc check_effective_target_keeps_null_pointer_checks { } {
@@ -704,7 +704,7 @@ proc check_effective_target_keeps_null_pointer_checks { } {
     }
     if { [istarget msp430-*-*]
          || [istarget avr-*-*] } {
-	return 1;
+	return 1;
     }
     return 0
 }
@@ -716,7 +716,7 @@ proc check_effective_target_keeps_null_pointer_checks { } {
 # Each individual perf tries to grab it
 # This causes problems with parallel test suite runs. Instead
 # limit us to 8 pages (32K), which should be good enough
-# for the small test programs. With the default settings
+# for the small test programs. With the default settings
 # this allows parallelism of 16 and higher of parallel gcc-auto-profile
 proc profopt-perf-wrapper { } {
     global srcdir
@@ -831,7 +831,7 @@ proc check_profiling_available { test_what } {
 	     || [istarget powerpc-*-eabi*]
 	     || [istarget powerpc-*-elf]
 	     || [istarget pru-*-*]
-	     || [istarget rx-*-*]
+	     || [istarget rx-*-*]
 	     || [istarget tic6x-*-elf]
 	     || [istarget visium-*-*]
 	     || [istarget xstormy16-*]
@@ -1020,7 +1020,7 @@ proc check_effective_target_tls_native {} {
     if { [istarget *-*-vxworks*] } {
 	return 0
     }
-
+
     return [check_no_messages_and_pattern tls_native "!emutls" assembly {
 	__thread int i;
 	int f (void) { return i; }
@@ -1036,7 +1036,7 @@ proc check_effective_target_tls_emulated {} {
     if { [istarget *-*-vxworks*] } {
 	return 1
     }
-
+
     return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
 	__thread int i;
 	int f (void) { return i; }
@@ -1082,7 +1082,7 @@ proc check_effective_target_function_sections {} {
     if { [istarget *-*-darwin*] } {
 	return 0
     }
-
+
     return [check_no_compiler_messages functionsections assembly {
  	void foo (void) { }
     } "-ffunction-sections"]
@@ -1104,7 +1104,7 @@ proc check_effective_target_trapping {} {
     } "-ftrapv"]
 }

-# Return 1 if compilation with -fgraphite is error-free for trivial
+# Return 1 if compilation with -fgraphite is error-free for trivial
 # code, 0 otherwise.

 proc check_effective_target_fgraphite {} {
@@ -1737,7 +1737,7 @@ proc check_effective_target_fortran_real_10 { } {
 # 0 otherwise.  This differs from check_effective_target_fortran_real_16
 # because _Float128 has the additional requirement that it be the
 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
-# have a corresponding Fortran kind on targets (PowerPC) that use some
+# have a corresponding Fortran kind on targets (PowerPC) that use some
 # other encoding for long double/TFmode/real(16).
 proc check_effective_target_fortran_real_c_float128 { } {
     return [check_no_compiler_messages fortran_real_c_float128 executable {
@@ -1889,6 +1889,28 @@ proc check_effective_target_riscv_a { } {
     }]
 }

+# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zalrsc { } {
+    return [check_no_compiler_messages riscv_ext_zalrsc assembly {
+       #ifndef __riscv_zalrsc
+       #error "Not __riscv_zalrsc"
+       #endif
+    }]
+}
+
+# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zaamo { } {
+    return [check_no_compiler_messages riscv_ext_zaamo assembly {
+       #ifndef __riscv_zaamo
+       #error "Not __riscv_zaamo"
+       #endif
+    }]
+}
+
 # Return 1 if the target arch supports the double precision floating point
 # extension, 0 otherwise.  Cache the result.

@@ -2010,7 +2032,7 @@ proc check_effective_target_riscv_v_ok { } {
 proc check_effective_target_riscv_zfh_ok { } {
     # If the target already supports zfh without any added options,
     # we may assume we can execute just fine.
-    # ??? Other cases we should consider:
+    # ??? Other cases we should consider:
     # - target / simulator already supports zfh extension - test for that.
     # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator
     if { [check_effective_target_riscv_zfh] } {
@@ -2083,7 +2105,7 @@ proc check_effective_target_riscv_zvbb_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } {
+    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } {
 	if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
 		#ifndef DEF
 		#error "Not DEF"
@@ -2142,6 +2164,30 @@ proc add_options_for_riscv_v { flags } {
     return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
 }

+proc add_options_for_riscv_zaamo { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+	# If there are multiple -march flags, we have to adjust all of them.
+	set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ]
+	return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zaamo] } {
+	return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zaamo"
+}
+
+proc add_options_for_riscv_zalrsc { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+	# If there are multiple -march flags, we have to adjust all of them.
+	set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ]
+	return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zalrsc] } {
+	return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zalrsc"
+}
+
 proc add_options_for_riscv_zfh { flags } {
     if { [lsearch $flags -march=*] >= 0 } {
 	# If there are multiple -march flags, we have to adjust all of them.
@@ -2945,7 +2991,7 @@ proc check_effective_target_long_double_ieee128 { } {
 	int main()
 	{
 	  _Float128 a2;
-	  long double b2;
+	  long double b2;
 	  if (sizeof (long double) != 16)
 	    return 1;
 	  b = one + two;
@@ -3409,7 +3455,7 @@ proc check_effective_target_ptr32plus { } {
     if { [istarget msp430-*-*] } {
         return 0
     }
-
+
     return [check_no_compiler_messages ptr32plus object {
 	int dummy[sizeof (void *) >= 4 ? 1 : -1];
     }]
@@ -4299,7 +4345,7 @@ proc check_effective_target_int128 { } {
     }]
 }

-# Return 1 if the target supports unsigned int->float conversion
+# Return 1 if the target supports unsigned int->float conversion
 #

 proc check_effective_target_vect_uintfloat_cvt { } {
@@ -5327,7 +5373,7 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
 	    if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
 		#include "arm_neon.h"
-		float32x2_t
+		float32x2_t
 		foo (float32x2_t a, float32x2_t b, float32x2_t c)
                 {
                   return vfma_f32 (a, b, c);
@@ -7840,7 +7886,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } {
 # promotion (unpacking) from chars to shorts.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_widen_sum_qi_to_hi { } {
     return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi {
       expr { [check_effective_target_vect_unpack]
@@ -7854,7 +7900,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } {
 # widening summation of *char* args into *int* result, 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_widen_sum_qi_to_si { } {
     return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
       expr { [istarget powerpc*-*-*]
@@ -7880,7 +7926,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } {
 		      && ![check_effective_target_aarch64_sve])
 		  || [is-effective-target arm_neon]
 		  || ([istarget s390*-*-*]
-		      && [check_effective_target_s390_vx]))
+		      && [check_effective_target_s390_vx]))
 	      || [istarget amdgcn-*-*] }}]
 }

@@ -8045,7 +8091,7 @@ proc check_effective_target_vect_udot_hi { } {
 	     || ([istarget mips*-*-*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget riscv*-*-*]
-		 && [check_effective_target_riscv_v])
+		 && [check_effective_target_riscv_v])
 	     || ([istarget loongarch*-*-*]
 		 && [check_effective_target_loongarch_sx]) }}]
 }
@@ -8099,11 +8145,11 @@ proc check_effective_target_vect_sdiv_pow2_si {} {
 }

 # Return 1 if the target plus current options supports a vector
-# demotion (packing) of shorts (to chars) and ints (to shorts)
+# demotion (packing) of shorts (to chars) and ints (to shorts)
 # using modulo arithmetic, 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_pack_trunc { } {
     return [check_cached_effective_target_indexed vect_pack_trunc {
       expr { [istarget powerpc*-*-*]
@@ -8126,7 +8172,7 @@ proc check_effective_target_vect_pack_trunc { } {
 # promotion (unpacking) of chars (to shorts) and shorts (to ints), 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_unpack { } {
     return [check_cached_effective_target_indexed vect_unpack {
       expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
@@ -8735,7 +8781,7 @@ proc check_effective_target_vector_alignment_reachable { } {

 proc check_effective_target_vector_alignment_reachable_for_64bit { } {
     set et_vector_alignment_reachable_for_64bit 0
-    if { [check_effective_target_vect_aligned_arrays]
+    if { [check_effective_target_vect_aligned_arrays]
 	 || [check_effective_target_natural_alignment_64] } {
 	set et_vector_alignment_reachable_for_64bit 1
     }
@@ -8836,7 +8882,7 @@ proc check_effective_target_vect_cond_mixed { } {
     return [check_cached_effective_target_indexed vect_cond_mixed {
       expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
 	     || [istarget aarch64*-*-*]
-	     || [istarget powerpc*-*-*]
+	     || [istarget powerpc*-*-*]
 	     || ([istarget arm*-*-*]
 		 && [check_effective_target_arm_neon_ok])
 	     || ([istarget mips*-*-*]
@@ -9509,14 +9555,14 @@ proc check_effective_target_sync_int_long { } {
       expr { [istarget ia64-*-*]
 	     || [istarget i?86-*-*] || [istarget x86_64-*-*]
 	     || [istarget aarch64*-*-*]
-	     || [istarget alpha*-*-*]
-	     || [istarget arm*-*-linux-*]
-	     || [istarget arm*-*-uclinuxfdpiceabi]
+	     || [istarget alpha*-*-*]
+	     || [istarget arm*-*-linux-*]
+	     || [istarget arm*-*-uclinuxfdpiceabi]
 	     || ([istarget arm*-*-*]
 		 && [check_effective_target_arm_acq_rel])
 	     || [istarget bfin*-*linux*]
 	     || [istarget hppa*-*linux*]
-	     || [istarget s390*-*-*]
+	     || [istarget s390*-*-*]
 	     || [istarget powerpc*-*-*]
 	     || [istarget cris-*-*]
 	     || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
@@ -9532,7 +9578,7 @@ proc check_effective_target_sync_int_long { } {
 proc check_effective_target_sync_int_long_stack { } {
     return [check_cached_effective_target sync_int_long_stack {
       expr { ![istarget nvptx*-*-*]
-	     && [check_effective_target_sync_int_long]
+	     && [check_effective_target_sync_int_long]
 	 }}]
 }

@@ -9545,13 +9591,13 @@ proc check_effective_target_sync_char_short { } {
       expr { [istarget aarch64*-*-*]
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*] || [istarget x86_64-*-*]
-	     || [istarget alpha*-*-*]
-	     || [istarget arm*-*-linux-*]
-	     || [istarget arm*-*-uclinuxfdpiceabi]
+	     || [istarget alpha*-*-*]
+	     || [istarget arm*-*-linux-*]
+	     || [istarget arm*-*-uclinuxfdpiceabi]
 	     || ([istarget arm*-*-*]
 		 && [check_effective_target_arm_acq_rel])
 	     || [istarget hppa*-*linux*]
-	     || [istarget s390*-*-*]
+	     || [istarget s390*-*-*]
 	     || [istarget powerpc*-*-*]
 	     || [istarget cris-*-*]
 	     || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
@@ -10443,7 +10489,7 @@ proc check_effective_target_sse { } {
 proc check_effective_target_sse2 { } {
     return [check_no_compiler_messages sse2 object {
 	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
-
+
 	__m128i _mm_srli_si128 (__m128i __A, int __N)
 	{
 	    return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
@@ -12512,14 +12558,14 @@ proc check_effective_target_autoincdec { } {
 #
 # This is used to restrict the stack-clash mitigation tests to
 # just those targets that have been explicitly supported.
-#
+#
 # In addition to the prologue work on those targets, each target's
 # properties should be described in the functions below so that
 # tests do not become a mess of unreadable target conditions.
-#
+#
 proc check_effective_target_supports_stack_clash_protection { } {

-    if { [istarget x86_64-*-*] || [istarget i?86-*-*]
+    if { [istarget x86_64-*-*] || [istarget i?86-*-*]
 	  || [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
 	  || [istarget aarch64*-**] || [istarget s390*-*-*]
 	  || [istarget loongarch64*-**] } {
@@ -13212,7 +13258,7 @@ main:
 	.byte 0
   } ""]
 }
-
+
 # Return 1 if this target has prog named "$prog", 0 otherwise.

 proc check_is_prog_name_available { prog } {
--
2.34.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
  2024-06-03 21:53 ` [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Patrick O'Neill
@ 2024-06-07 23:04   ` Jeff Law
  2024-06-10 16:39     ` Patrick O'Neill
  0 siblings, 1 reply; 13+ messages in thread
From: Jeff Law @ 2024-06-07 23:04 UTC (permalink / raw)
  To: Patrick O'Neill, gcc-patches; +Cc: palmer, gnu-toolchain



On 6/3/24 3:53 PM, Patrick O'Neill wrote:
> Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather
> 	than A.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather
> 	than A.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
> 	* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather
> 	than A.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
> 	* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
> 	* lib/target-supports.exp: Add testsuite infrastructure support for
> 	Zaamo and Zalrsc.
So there's a lot of whitespace changes going on in target-supports.exp 
that make it harder to find the real changes.

There's always a bit of a judgement call for that kind of thing.  This 
one probably goes past would generally recommend, meaning that the 
formatting stuff would be a separate patch.

A reasonable starting point would be if you're not changing the function 
in question, then fixing formatting in it probably should be a distinct 
patch.

You probably should update the docs in sourcebuild.texi for the new 
target-supports tests.

So OK for the trunk (including the whitespace fixes) with a suitable 
change to sourcebuild.texi.

jeff

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
  2024-06-07 23:04   ` Jeff Law
@ 2024-06-10 16:39     ` Patrick O'Neill
  2024-06-11 18:21       ` Patrick O'Neill
  0 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-10 16:39 UTC (permalink / raw)
  To: Jeff Law, gcc-patches; +Cc: palmer, gnu-toolchain


On 6/7/24 16:04, Jeff Law wrote:
>
>
> On 6/3/24 3:53 PM, Patrick O'Neill wrote:
>> Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather 
>> than A.
>>     * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc 
>> rather
>>     than A.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo 
>> rather
>>     than A.
>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
>>     * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use 
>> Zalrsc rather
>>     than A.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
>>     * lib/target-supports.exp: Add testsuite infrastructure support for
>>     Zaamo and Zalrsc.
> So there's a lot of whitespace changes going on in target-supports.exp 
> that make it harder to find the real changes.
>
> There's always a bit of a judgement call for that kind of thing. This 
> one probably goes past would generally recommend, meaning that the 
> formatting stuff would be a separate patch.
>
> A reasonable starting point would be if you're not changing the 
> function in question, then fixing formatting in it probably should be 
> a distinct patch.
>
> You probably should update the docs in sourcebuild.texi for the new 
> target-supports tests.
>
> So OK for the trunk (including the whitespace fixes) with a suitable 
> change to sourcebuild.texi.

Sorry about that - the whitespace changes snuck in when resolving a 
merge conflict and were unintentional.

I'll post a v3 with the sourcebuild.texi changes and patch 3/3 changes 
later today.

I'll split the target-supports.exp trailing whitespace removal into a 
separate patch after this series lands.

Patrick

>
> jeff

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
  2024-06-10 16:39     ` Patrick O'Neill
@ 2024-06-11 18:21       ` Patrick O'Neill
  2024-06-12 18:14         ` Jeff Law
  0 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-11 18:21 UTC (permalink / raw)
  To: Jeff Law, gcc-patches; +Cc: palmer, gnu-toolchain


On 6/10/24 09:39, Patrick O'Neill wrote:
>
> On 6/7/24 16:04, Jeff Law wrote:
>>
>>
>> On 6/3/24 3:53 PM, Patrick O'Neill wrote:
>>> Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>>     * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather 
>>> than A.
>>>     * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use 
>>> Zalrsc rather
>>>     than A.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo 
>>> rather
>>>     than A.
>>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
>>>     * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use 
>>> Zalrsc rather
>>>     than A.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
>>>     * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
>>>     * lib/target-supports.exp: Add testsuite infrastructure support for
>>>     Zaamo and Zalrsc.
>> So there's a lot of whitespace changes going on in 
>> target-supports.exp that make it harder to find the real changes.
>>
>> There's always a bit of a judgement call for that kind of thing. This 
>> one probably goes past would generally recommend, meaning that the 
>> formatting stuff would be a separate patch.
>>
>> A reasonable starting point would be if you're not changing the 
>> function in question, then fixing formatting in it probably should be 
>> a distinct patch. 
[... snip ...]
> I'll split the target-supports.exp trailing whitespace removal into a 
> separate patch after this series lands.

I made the whitespace cleanup patch (trailing whitespace, leading groups 
of 8 spaces -> tabs) for
target-supports.exp and got a diff of 584 lines.

Is this still worth doing or will it be too disruptive for 
rebasing/other people's development?

Patrick


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support
  2024-06-11 18:21       ` Patrick O'Neill
@ 2024-06-12 18:14         ` Jeff Law
  0 siblings, 0 replies; 13+ messages in thread
From: Jeff Law @ 2024-06-12 18:14 UTC (permalink / raw)
  To: Patrick O'Neill, gcc-patches; +Cc: palmer, gnu-toolchain



On 6/11/24 12:21 PM, Patrick O'Neill wrote:

> 
> I made the whitespace cleanup patch (trailing whitespace, leading groups 
> of 8 spaces -> tabs) for
> target-supports.exp and got a diff of 584 lines.
> 
> Is this still worth doing or will it be too disruptive for rebasing/ 
> other people's development?
I don't think it's overly disruptive.  This stuff doesn't have a lot of 
churn.  It'd be different if you were reformatting the whole tree :-)

Consider those fixes pre-approved.

jeff


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns
  2024-06-03 21:53 [PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support Patrick O'Neill
  2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
  2024-06-03 21:53 ` [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Patrick O'Neill
@ 2024-06-03 21:53 ` Patrick O'Neill
  2024-06-07 23:11   ` Jeff Law
  2 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2024-06-03 21:53 UTC (permalink / raw)
  To: gcc-patches; +Cc: jeffreyalaw, palmer, gnu-toolchain, Patrick O'Neill

All amo<op> patterns can be represented with lrsc sequences.
Add these patterns as a fallback when Zaamo is not enabled.

gcc/ChangeLog:

	* config/riscv/sync.md (atomic_<atomic_optab><mode>): New expand pattern.
	(amo_atomic_<atomic_optab><mode>): Rename amo pattern.
	(atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
	(lrsc_atomic_<atomic_optab><mode>): New expand pattern.
	(amo_atomic_fetch_<atomic_optab><mode>): Rename amo pattern.
	(lrsc_atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
	(atomic_exchange<mode>): New expand pattern.
	(amo_atomic_exchange<mode>): Rename amo pattern.
	(lrsc_atomic_exchange<mode>): New lrsc sequence pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test.
	* gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test.
	* gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test.
	* gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test.
	* gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test.
	* gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
------
rv64imfdc_zalrsc has the same testsuite results as rv64imafdc after this
patch is applied.
---
AFAIK there isn't a way to subtract an extension similar to dg-add-options.
As a result I needed to specify a -march string for
amo-zaamo-preferred-over-zalrsc.c instead of using testsuite infra.
---
 gcc/config/riscv/sync.md                      | 124 +++++++++++++++++-
 .../riscv/amo-zaamo-preferred-over-zalrsc.c   |  17 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-1.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-2.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-3.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-4.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-5.c   |  19 +++
 7 files changed, 231 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index c9544176ead..4df9d0b5a5f 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -86,7 +86,24 @@
     DONE;
   })

-(define_insn "atomic_<atomic_optab><mode>"
+;; AMO ops
+
+(define_expand "atomic_<atomic_optab><mode>"
+  [(any_atomic:GPR (match_operand:GPR 0 "memory_operand")    ;; mem location
+		   (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op
+   (match_operand:SI 2 "const_int_operand")]		     ;; model
+  "TARGET_ZAAMO || TARGET_ZALRSC"
+{
+  if (TARGET_ZAAMO)
+    emit_insn (gen_amo_atomic_<atomic_optab><mode> (operands[0], operands[1],
+						    operands[2]));
+  else
+    emit_insn (gen_lrsc_atomic_<atomic_optab><mode> (operands[0], operands[1],
+						     operands[2]));
+  DONE;
+})
+
+(define_insn "amo_atomic_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+A")
 	(unspec_volatile:GPR
 	  [(any_atomic:GPR (match_dup 0)
@@ -98,7 +115,44 @@
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])

-(define_insn "atomic_fetch_<atomic_optab><mode>"
+(define_insn "lrsc_atomic_<atomic_optab><mode>"
+  [(set (match_operand:GPR 0 "memory_operand" "+A")
+	(unspec_volatile:GPR
+	  [(any_atomic:GPR (match_dup 0)
+		     (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
+	   (match_operand:SI 2 "const_int_operand")] ;; model
+	 UNSPEC_SYNC_OLD_OP))
+   (clobber (match_scratch:GPR 3 "=&r"))]	     ;; tmp_1
+  "!TARGET_ZAAMO && TARGET_ZALRSC"
+  {
+    return "1:\;"
+	   "lr.<amo>%I2\t%3, %0\;"
+	   "<insn>\t%3, %3, %1\;"
+	   "sc.<amo>%J2\t%3, %3, %0\;"
+	   "bnez\t%3, 1b";
+  }
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 16))])
+
+;; AMO fetch ops
+
+(define_expand "atomic_fetch_<atomic_optab><mode>"
+  [(match_operand:GPR 0 "register_operand")		     ;; old value at mem
+   (any_atomic:GPR (match_operand:GPR 1 "memory_operand")    ;; mem location
+		   (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op
+   (match_operand:SI 3 "const_int_operand")]		     ;; model
+  "TARGET_ZAAMO || TARGET_ZALRSC"
+  {
+    if (TARGET_ZAAMO)
+      emit_insn (gen_amo_atomic_fetch_<atomic_optab><mode> (operands[0], operands[1],
+							    operands[2], operands[3]));
+    else
+      emit_insn (gen_lrsc_atomic_fetch_<atomic_optab><mode> (operands[0], operands[1],
+							     operands[2], operands[3]));
+    DONE;
+  })
+
+(define_insn "amo_atomic_fetch_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
 	(match_operand:GPR 1 "memory_operand" "+A"))
    (set (match_dup 1)
@@ -112,6 +166,27 @@
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])

+(define_insn "lrsc_atomic_fetch_<atomic_optab><mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=&r")
+	(match_operand:GPR 1 "memory_operand" "+A"))
+   (set (match_dup 1)
+	(unspec_volatile:GPR
+	  [(any_atomic:GPR (match_dup 1)
+		     (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
+	   (match_operand:SI 3 "const_int_operand")] ;; model
+	 UNSPEC_SYNC_OLD_OP))
+   (clobber (match_scratch:GPR 4 "=&r"))]	  ;; tmp_1
+  "!TARGET_ZAAMO && TARGET_ZALRSC"
+  {
+    return "1:\;"
+	   "lr.<amo>%I3\t%0, %1\;"
+	   "<insn>\t%4, %0, %2\;"
+	   "sc.<amo>%J3\t%4, %4, %1\;"
+	   "bnez\t%4, 1b";
+  }
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 20))])
+
 (define_insn "subword_atomic_fetch_strong_<atomic_optab>"
   [(set (match_operand:SI 0 "register_operand" "=&r")		   ;; old value at mem
 	(match_operand:SI 1 "memory_operand" "+A"))		   ;; mem location
@@ -248,7 +323,23 @@
   DONE;
 })

-(define_insn "atomic_exchange<mode>"
+(define_expand "atomic_exchange<mode>"
+  [(match_operand:GPR 0 "register_operand")  ;; old value at mem
+   (match_operand:GPR 1 "memory_operand")    ;; mem location
+   (match_operand:GPR 2 "register_operand")  ;; value for op
+   (match_operand:SI 3 "const_int_operand")] ;; model
+  "TARGET_ZAAMO || TARGET_ZALRSC"
+  {
+    if (TARGET_ZAAMO)
+      emit_insn (gen_amo_atomic_exchange<mode> (operands[0], operands[1],
+					    operands[2], operands[3]));
+    else
+      emit_insn (gen_lrsc_atomic_exchange<mode> (operands[0], operands[1],
+					     operands[2], operands[3]));
+    DONE;
+  })
+
+(define_insn "amo_atomic_exchange<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&r")
 	(unspec_volatile:GPR
 	  [(match_operand:GPR 1 "memory_operand" "+A")
@@ -261,6 +352,26 @@
   [(set_attr "type" "atomic")
    (set (attr "length") (const_int 4))])

+(define_insn "lrsc_atomic_exchange<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=&r")
+	(unspec_volatile:GPR
+	  [(match_operand:GPR 1 "memory_operand" "+A")
+	   (match_operand:SI 3 "const_int_operand")] ;; model
+	  UNSPEC_SYNC_EXCHANGE))
+   (set (match_dup 1)
+	(match_operand:GPR 2 "register_operand" "0"))
+   (clobber (match_scratch:GPR 4 "=&r"))]	  ;; tmp_1
+  "!TARGET_ZAAMO && TARGET_ZALRSC"
+  {
+    return "1:\;"
+	   "lr.<amo>%I3\t%4, %1\;"
+	   "sc.<amo>%J3\t%0, %0, %1\;"
+	   "bnez\t%0, 1b\;"
+	   "mv\t%0, %4";
+  }
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 20))])
+
 (define_expand "atomic_exchange<mode>"
   [(match_operand:SHORT 0 "register_operand") ;; old value at mem
    (match_operand:SHORT 1 "memory_operand")   ;; mem location
@@ -516,7 +627,7 @@
   [(match_operand:QI 0 "register_operand" "")    ;; bool output
    (match_operand:QI 1 "memory_operand" "+A")    ;; memory
    (match_operand:SI 2 "const_int_operand" "")]  ;; model
-  "TARGET_ZALRSC"
+  "TARGET_ZAAMO || TARGET_ZALRSC"
 {
   /* We have no QImode atomics, so use the address LSBs to form a mask,
      then use an aligned SImode atomic.  */
@@ -537,7 +648,10 @@
   rtx shifted_set = gen_reg_rtx (SImode);
   riscv_lshift_subword (QImode, set, shift, &shifted_set);

-  emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
+  if (TARGET_ZAAMO)
+    emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
+  else if (TARGET_ZALRSC)
+    emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));

   emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
 					 gen_lowpart (QImode, shift)));
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
new file mode 100644
index 00000000000..1c124c2b8b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalrsc } */
+/* { dg-add-options riscv_zaamo } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	amoadd\.w\tzero,a1,0\(a0\)
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
new file mode 100644
index 00000000000..3cd6ce04830
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	1:
+**	lr.w\ta5, 0\(a0\)
+**	add\ta5, a5, a1
+**	sc.w\ta5, a5, 0\(a0\)
+**      bnez\ta5, 1b
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
new file mode 100644
index 00000000000..d7371dac301
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	1:
+**	lr.w.aq\ta5, 0\(a0\)
+**	add\ta5, a5, a1
+**	sc.w\ta5, a5, 0\(a0\)
+**      bnez\ta5, 1b
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
new file mode 100644
index 00000000000..25060b0894f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	1:
+**	lr.w\ta5, 0\(a0\)
+**	add\ta5, a5, a1
+**	sc.w.rl\ta5, a5, 0\(a0\)
+**      bnez\ta5, 1b
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
new file mode 100644
index 00000000000..7cf9357fdbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	1:
+**	lr.w.aq\ta5, 0\(a0\)
+**	add\ta5, a5, a1
+**	sc.w.rl\ta5, a5, 0\(a0\)
+**      bnez\ta5, 1b
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c
new file mode 100644
index 00000000000..df761892493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+**	1:
+**	lr.w.aqrl\ta5, 0\(a0\)
+**	add\ta5, a5, a1
+**	sc.w.rl\ta5, a5, 0\(a0\)
+**      bnez\ta5, 1b
+**	ret
+*/
+void foo (int* bar, int* baz)
+{
+  __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
+}
--
2.34.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns
  2024-06-03 21:53 ` [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns Patrick O'Neill
@ 2024-06-07 23:11   ` Jeff Law
  0 siblings, 0 replies; 13+ messages in thread
From: Jeff Law @ 2024-06-07 23:11 UTC (permalink / raw)
  To: Patrick O'Neill, gcc-patches; +Cc: palmer, gnu-toolchain



On 6/3/24 3:53 PM, Patrick O'Neill wrote:
> All amo<op> patterns can be represented with lrsc sequences.
> Add these patterns as a fallback when Zaamo is not enabled.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/sync.md (atomic_<atomic_optab><mode>): New expand pattern.
> 	(amo_atomic_<atomic_optab><mode>): Rename amo pattern.
> 	(atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
> 	(lrsc_atomic_<atomic_optab><mode>): New expand pattern.
> 	(amo_atomic_fetch_<atomic_optab><mode>): Rename amo pattern.
> 	(lrsc_atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
> 	(atomic_exchange<mode>): New expand pattern.
> 	(amo_atomic_exchange<mode>): Rename amo pattern.
> 	(lrsc_atomic_exchange<mode>): New lrsc sequence pattern.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test.
> 	* gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test.
> 	* gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test.
> 	* gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test.
> 	* gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test.
> 	* gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test.
> 
> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
> ------
> rv64imfdc_zalrsc has the same testsuite results as rv64imafdc after this
> patch is applied.
> ---
> AFAIK there isn't a way to subtract an extension similar to dg-add-options.
> As a result I needed to specify a -march string for
> amo-zaamo-preferred-over-zalrsc.c instead of using testsuite infra.
I believe you are correct.



> diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
> new file mode 100644
> index 00000000000..1c124c2b8b1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
[ ... ]
Not a big fan of the function-bodies tests.  If we're going to use them, 
we need to be especially careful about requiring specific registers so 
that we're not stuck adjusting them all the time due to changes in the 
regsiter allocator, optimizers, etc.

> diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
> new file mode 100644
> index 00000000000..3cd6ce04830
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
> @@ -0,0 +1,19 @@
> +/* { dg-do compile } */
> +/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.  */
> +/* { dg-options "-O3 -march=rv64id_zalrsc" } */
> +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** foo:
> +**	1:
> +**	lr.w\ta5, 0\(a0\)
> +**	add\ta5, a5, a1
> +**	sc.w\ta5, a5, 0\(a0\)
> +**      bnez\ta5, 1b
> +**	ret
> +*/
> +void foo (int* bar, int* baz)
> +{
> +  __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
> +}
This one is a good example.  We could just as easily use a variety of 
registers other than a5 for the temporary.

Obviously for registers that hold the incoming argument or an outgoing 
result, we can be more strict.

If you could take a look at the added tests and generalize the registers 
it'd be appreciated.  OK with that adjustment.

jeff



^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2024-06-12 18:14 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-06-03 21:53 [PATCH v2 0/3] RISC-V: Add basic Zaamo and Zalrsc support Patrick O'Neill
2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
2024-06-04  3:00   ` Kito Cheng
2024-06-04 17:30     ` Patrick O'Neill
2024-06-04 21:27       ` Andrew Waterman
2024-06-07 22:35   ` Jeff Law
2024-06-03 21:53 ` [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Patrick O'Neill
2024-06-07 23:04   ` Jeff Law
2024-06-10 16:39     ` Patrick O'Neill
2024-06-11 18:21       ` Patrick O'Neill
2024-06-12 18:14         ` Jeff Law
2024-06-03 21:53 ` [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns Patrick O'Neill
2024-06-07 23:11   ` Jeff Law

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