From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id D6A2B3858D28 for ; Thu, 6 Apr 2023 14:21:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D6A2B3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=adacore.com Received: by mail-wr1-x429.google.com with SMTP id m2so39694905wrh.6 for ; Thu, 06 Apr 2023 07:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore.com; s=google; t=1680790917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lzlkitEtmWIHBpOzAjqRQONVU5g75mH7YROi3+8eNzo=; b=ioj8Qk7EHQhgMTE749/omyG6ZwSWIInt0KqI4iYFDWmFLDsISC2c+XgWyNgHiP6tiQ TJjGJCzdmQzPPdyyDFpNfoBGRRpkWkAKDf8efC5E/CWrVmEay8XadgKicpvXL8dkB/5g 1Nq+6k0nx3quSpdZ0txqudFifoEXG5M3rBFjFOfXJu4Sm3VDORhzJM1UjID7QG58KXnV G1gdRQ0yG/+q764EPzzpQSps4wzREiSn0xvpOgkk4pFDBTlYjmtzBndMYL8101OTv/YP 4YmsGJ9RGM+UQx6XtCb6dT9PB7JkUVRMYXGV1p3WiEz/eMOIJAQkRMQRiKUOTVzjmnk8 VCDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680790917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lzlkitEtmWIHBpOzAjqRQONVU5g75mH7YROi3+8eNzo=; b=tthAbjaNtIlVkFsq6/GlsnNR5wJVPtwsiMHzPuz4oYfk1T8kUBWURPqiUVOKmC8lfM 98jEGIOtmoOntfG8y86ArLGPooUjSkEosoHL5HLjisKLtjJ9LvO+BG9cGfecAglll+jd P8HdhhKnUWMoXBOa4+Mt22EiPF/WDga9RTz9EcmzJIYgdgxC/k0OaPZGgMozdsm8NHli iP1hStuIqfIWb3Mk3mYGmHnd5ZTLkhEuNAQr4yU5a6xZLwHU6GFeChEYhMsBWiK8tTQT vU3uVBBX8noU+tHq+u6dfLPmiOss7/SHBnU03mwnpQNjPM4X3p0RBSwMy2GP5txIppfV /a3Q== X-Gm-Message-State: AAQBX9dayLiHuXwkZimlxCLsuuVh5I/uUxStcjifQKOvnpAFJpdRmcrX s976Je6AfXaBgw/uuhX4uW43Hg== X-Google-Smtp-Source: AKy350biwbBE8qpCEB06E2a4Ry8BENHKC3L8r5Cjz0Vjv6gbzXjyzX7wq6iQpIa9Bbcp7WtW/AE1MA== X-Received: by 2002:adf:eacd:0:b0:2da:a4df:d04c with SMTP id o13-20020adfeacd000000b002daa4dfd04cmr5877021wrn.19.1680790917531; Thu, 06 Apr 2023 07:21:57 -0700 (PDT) Received: from fomalhaut.localnet ([2a01:e0a:8d5:d990:e654:e8ff:fe8f:2ce6]) by smtp.gmail.com with ESMTPSA id h11-20020adff18b000000b002e40d124460sm1854406wro.97.2023.04.06.07.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 07:21:57 -0700 (PDT) From: Eric Botcazou X-Google-Original-From: Eric Botcazou To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org, Jeff Law , Richard Biener , Richard Sandiford , gcc-patches@gcc.gnu.org Subject: Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040] Date: Thu, 06 Apr 2023 16:21:56 +0200 Message-ID: <3412470.QJadu78ljV@fomalhaut> In-Reply-To: References: <2220543.iZASKD2KPV@fomalhaut> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > If the > (and:SI (subreg:SI (reg:HI xxx) 0) (const_int 0x84c)) > to > (subreg:SI (and:HI (reg:HI xxx) (const_int 0x84c)) 0) > transformation is kosher for WORD_REGISTER_OPERATIONS, then I guess the > invalid operation is then in > simplify_context::simplify_binary_operation_1 > case AND: > ... > if (HWI_COMPUTABLE_MODE_P (mode)) > { > HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, mode); > HOST_WIDE_INT nzop1; > if (CONST_INT_P (trueop1)) > { > HOST_WIDE_INT val1 = INTVAL (trueop1); > /* If we are turning off bits already known off in OP0, we > need not do an AND. */ > if ((nzop0 & ~val1) == 0) > return op0; > } > We have there op0==trueop0 (reg:HI 175) and op1==trueop1 (const_int 2124 > [0x84c]). > We then for integral? modes smaller than word_mode would then need to > actually check nonzero_bits in the word_mode (on paradoxical subreg of > trueop0?). If INTVAL (trueop1) is >= 0, then I think just doing > nonzero_bits in the wider mode would be all we need (although the > subsequent (nzop1 & nzop0) == 0 case probably wants to have the current > nonzero_bits calls), not really sure what for WORD_REGISTER_OPERATIONS > means AND with a constant which has the most significant bit set for the > upper bits. Yes, I agree that there is a tension between this AND case and the swapping done in the combiner for WORD_REGISTER_OPERATIONS. I also agree that it would make sense do call nonzero_bits on word_mode instead of mode here in this case because AND is a word_register_operation_p. > So, perhaps just in the return op0; case add further code for > WORD_REGISTER_OPERATIONS and sub-word modes which will call nonzero_bits > again for the word mode and decide if it is still safe. Does it work to just replace mode by word_mode in the calls to nonzero_bits? > That patch doesn't change anything at all on the testcase, it is still > miscompiled. OK, too bad, thanks for trying it! -- Eric Botcazou