Re: [PATCH] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[Robin Dapp <rdapp.gcc@gmail.com>]

Hi Lehua,

I once had different comments for those but either I never pushed them
or they got buried in the process of refactoring.  The explanatory
comment explaining vlmax is also in "nowhere land" below autovec_use_vlmax_p.
(it says vsetvli instead of vsetvl as well...)  It would be useful
to move it to above the function comments you touch.

> +/* Emit RVV insn which vl is the number of units of the vector mode.
> +   This function can only be used before LRA pass or for VLS_AVL_IMM modes.  */

Emit an RVV insn with a vector length that equals the number of units of
the vector mode.  For VLA modes this corresponds to VLMAX.

Unless the vector length can be encoded in the vsetivl[i] instruction this
function must only be used as long as we can create pseudo registers.
This is because it will set a pseudo register to VLMAX using vsetvl and
use this as definition for the vector length.


Besides, we could add a const_vlmax_p () || can_create_pseudo_p assert here?


> +/* Like emit_vlmax_insn but can be only used after LRA pass that can't create
> +   pseudo register.  */

Like emit_vlmax_insn but must only be used when we cannot create pseudo
registers anymore.  This function, however, takes a predefined vector
length from the value in VL.

> +/* Emit RVV insn which vl is the VL argument.  */
> +emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)

I think I renamed this to emit_len_insn or something before but Juzhe didn't
like it ;)

How about something like:
Emit an RVV insn with a predefined vector length.  Contrary to emit_vlmax_insn
the instruction's vector length is not deduced from its mode but taken from 
the value in VL.

Regards
 Robin