From: Dimitar Dimitrov <dimitar@dinux.eu>
To: gcc-patches@gcc.gnu.org
Cc: Dimitar Dimitrov <dimitar@dinux.eu>
Subject: [COMMITTED 2/9] pru: Implement zero fill for 64-bit registers
Date: Tue, 7 May 2024 10:22:34 +0300 [thread overview]
Message-ID: <350fe00fd7177b6883bcdb71149ef02894593402.1715065537.git.dimitar@dinux.eu> (raw)
In-Reply-To: <cover.1715065537.git.dimitar@dinux.eu>
Loading a constant zero in a 64-bit register now takes one instead of
two instructions.
gcc/ChangeLog:
* config/pru/pru.md: New pattern alternative for zero-filling
64-bit registers.
gcc/testsuite/ChangeLog:
* gcc.target/pru/mov-0.c: New test.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
gcc/config/pru/pru.md | 18 ++++++++++--------
gcc/testsuite/gcc.target/pru/mov-0.c | 19 +++++++++++++++++++
2 files changed, 29 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/pru/mov-0.c
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 8393d8f9607..0123952aa9e 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -248,8 +248,8 @@ (define_insn "prumov<mode>"
; Forcing DI reg alignment (akin to microblaze's HARD_REGNO_MODE_OK)
; does not seem efficient, and will violate TI ABI.
(define_insn "mov<mode>"
- [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
- (match_operand:MOV64 1 "general_operand" "r,m,Um,r,T,J,nF"))]
+ [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r,r")
+ (match_operand:MOV64 1 "general_operand" "r,m,Z,Um,r,T,J,nF"))]
""
{
switch (which_alternative)
@@ -259,8 +259,10 @@ (define_insn "mov<mode>"
case 1:
return "lb%B1o\\t%b0, %1, %S1";
case 2:
- return "fill\\t%F0, 8";
+ return "zero\\t%F0, 8";
case 3:
+ return "fill\\t%F0, 8";
+ case 4:
/* careful with overlapping source and destination regs. */
gcc_assert (GP_REG_P (REGNO (operands[0])));
gcc_assert (GP_REG_P (REGNO (operands[1])));
@@ -268,18 +270,18 @@ (define_insn "mov<mode>"
return "mov\\t%N0, %N1\;mov\\t%F0, %F1";
else
return "mov\\t%F0, %F1\;mov\\t%N0, %N1";
- case 4:
- return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
case 5:
- return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+ return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
case 6:
+ return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+ case 7:
return "ldi32\\t%F0, %w1\;ldi32\\t%N0, %W1";
default:
gcc_unreachable ();
}
}
- [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
- (set_attr "length" "4,4,4,8,8,8,16")])
+ [(set_attr "type" "st,ld,alu,alu,alu,alu,alu,alu")
+ (set_attr "length" "4,4,4,4,8,8,8,16")])
;
; load_multiple pattern(s).
diff --git a/gcc/testsuite/gcc.target/pru/mov-0.c b/gcc/testsuite/gcc.target/pru/mov-0.c
new file mode 100644
index 00000000000..0190be36fa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/mov-0.c
@@ -0,0 +1,19 @@
+/* Loading a register with constant 0 integer value. */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int
+test_set_0_si (void)
+{
+ /* Since zero-extension is free, "zero" fill is not implemented for SI. */
+ /* { dg-final { scan-assembler "ldi\\tr14(.b0)?, 0" } } */
+ return 0;
+}
+
+long long
+test_set_0_di (void)
+{
+ /* { dg-final { scan-assembler "zero\\tr14(.b0)?, 8" } } */
+ return 0;
+}
--
2.45.0
next prev parent reply other threads:[~2024-05-07 7:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 7:22 [COMMITTED 0/9] Small cleanups and improvements for PRU backend Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 1/9] pru: Implement TARGET_ADDRESS_COST Dimitar Dimitrov
2024-05-07 7:22 ` Dimitar Dimitrov [this message]
2024-05-07 7:22 ` [COMMITTED 3/9] pru: Optimize the extzv and insv patterns Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 4/9] pru: Add pattern variants for zero extending destination Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 5/9] pru: Skip register save if function will not return Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 6/9] pru: Drop usage of ATTRIBUTE_UNUSED Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 7/9] pru: Use HOST_WIDE_INT_1U macro Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 8/9] pru: Refactor to use passes definition file Dimitar Dimitrov
2024-05-07 7:22 ` [COMMITTED 9/9] pru: New validation pass for minrt Dimitar Dimitrov
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