diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm index 560df13d119d740beb56d2b9f2cd33be40a41db9..8cde4f43ee65184c316ab4c7e5b78c5bb0c6e7bb 100644 --- a/gcc/ChangeLog.arm +++ b/gcc/ChangeLog.arm @@ -1,3 +1,17 @@ +2017-06-01 Thomas Preud'homme + + Backport from mainline + 2017-05-03 Thomas Preud'homme + + * config/arm/iterators.md (CCSI): New mode iterator. + (arch): New mode attribute. + * config/arm/sync.md (atomic_compare_and_swap_1): Rename into ... + (atomic_compare_and_swap_1): This and ... + (atomic_compare_and_swap_1): This. Use CCSI + code iterator for success result mode. + * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use + the corresponding new insn generators. + 2017-05-31 Prakhar Bahuguna Backport from mainline diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7b7558fc4e1e797e099a8233c52e369aa7af0dad..635468dd071e09af5bb8139f6566ac51e232db6b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -29049,17 +29049,32 @@ arm_expand_compare_and_swap (rtx operands[]) gcc_unreachable (); } - switch (mode) + if (TARGET_THUMB1) { - case QImode: gen = gen_atomic_compare_and_swapqi_1; break; - case HImode: gen = gen_atomic_compare_and_swaphi_1; break; - case SImode: gen = gen_atomic_compare_and_swapsi_1; break; - case DImode: gen = gen_atomic_compare_and_swapdi_1; break; - default: - gcc_unreachable (); + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swapt1qi_1; break; + case HImode: gen = gen_atomic_compare_and_swapt1hi_1; break; + case SImode: gen = gen_atomic_compare_and_swapt1si_1; break; + case DImode: gen = gen_atomic_compare_and_swapt1di_1; break; + default: + gcc_unreachable (); + } + } + else + { + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swap32qi_1; break; + case HImode: gen = gen_atomic_compare_and_swap32hi_1; break; + case SImode: gen = gen_atomic_compare_and_swap32si_1; break; + case DImode: gen = gen_atomic_compare_and_swap32di_1; break; + default: + gcc_unreachable (); + } } - bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM); + bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CC_Zmode, CC_REGNUM); emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f)); if (mode == QImode || mode == HImode) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 572affc3fdc158606340a7b4926f437fb9fddf7d..c1d462cdf4cd7dbfe6518ad6f3cf41e84009127d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -45,6 +45,9 @@ ;; A list of the 32bit and 64bit integer modes (define_mode_iterator SIDI [SI DI]) +;; A list of atomic compare and swap success return modes +(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) + ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) @@ -370,6 +373,10 @@ ;; Mode attributes ;;---------------------------------------------------------------------------- +;; Determine name of atomic compare and swap from success result mode. This +;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. +(define_mode_attr arch [(CC_Z "32") (SI "t1")]) + ;; Determine element size suffix from vector mode. (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 64a12d762112a1e8eb3907d353071187765153a2..511bb4364c8a5a373a3067a23e812ca3878c1b25 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -191,9 +191,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory @@ -223,9 +223,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2)