From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94604 invoked by alias); 1 Jun 2017 16:03:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 94570 invoked by uid 89); 1 Jun 2017 16:02:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=aim, HX-Envelope-From:sk:thomas., 2239, adversely X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Jun 2017 16:02:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC82A344 for ; Thu, 1 Jun 2017 09:02:53 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 890683F578 for ; Thu, 1 Jun 2017 09:02:53 -0700 (PDT) Subject: [arm-embedded] [PATCH, GCC, ARM/embedded-6/7-branch] Set mode for success result of atomic compare and swap To: gcc-patches@gcc.gnu.org References: <58F7674C.6050006@foss.arm.com> <8a356417-3ccd-f6c7-ee69-7b19719b4c44@foss.arm.com> <5909A598.4020106@foss.arm.com> From: Thomas Preudhomme Message-ID: <35227c34-08e2-3d33-4091-7ac169d4135c@foss.arm.com> Date: Thu, 01 Jun 2017 16:03:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <5909A598.4020106@foss.arm.com> Content-Type: multipart/mixed; boundary="------------6F5E99133647E31965D1D707" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg00057.txt.bz2 This is a multi-part message in MIME format. --------------6F5E99133647E31965D1D707 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 14267 Hi, We have decided to apply the following patch to the embedded-6-branch and embedded-7-branch to fix a genrecog warning when processing sync.md. ChangeLog entry is as follows: 2017-05-03 Thomas Preud'homme Backport from mainline 2017-05-03 Thomas Preud'homme gcc/ * config/arm/iterators.md (CCSI): New mode iterator. (arch): New mode attribute. * config/arm/sync.md (atomic_compare_and_swap_1): Rename into ... (atomic_compare_and_swap_1): This and ... (atomic_compare_and_swap_1): This. Use CCSI code iterator for success result mode. * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use the corresponding new insn generators. Best regards, Thomas On 03/05/17 10:40, Kyrill Tkachov wrote: > Hi Thomas, > > On 03/05/17 10:39, Thomas Preudhomme wrote: >> Hi Kyrill, >> >> On 19/04/17 14:34, Kyrill Tkachov wrote: >>> Hi Thomas, >>> >>> On 12/04/17 09:59, Thomas Preudhomme wrote: >>>> Hi, >>>> >>>> Currently atomic_compare_and_swap_1 define_insn do not have a mode >>>> set for the destination of the set indicating the success result of the >>>> instruction. This is because the operand can be either a CC_Z register >>>> (for 32-bit targets) or a SI register (for 16-bit Thumb targets). This >>>> result in lack of checking for the mode. >>>> >>>> This commit use a new CCSI iterator to solve this issue while avoiding >>>> duplication of the patterns. The insn name are kept unique by using >>>> attributes tied to the iterator (SIDI:mode and CCSI:arch) instead of >>>> usign the builtin mode attribute. Expander arm_expand_compare_and_swap >>>> is also adapted accordingly. >>>> >>>> ChangeLog entry is as follows: >>>> >>>> *** gcc/ChangeLog *** >>>> >>>> 2017-04-11 Thomas Preud'homme >>>> >>>> * config/arm/iterators.md (CCSI): New mode iterator. >>>> (arch): New mode attribute. >>>> * config/arm/sync.md (atomic_compare_and_swap_1): Rename into ... >>>> (atomic_compare_and_swap_1): This and ... >>>> (atomic_compare_and_swap_1): This. Use CCSI >>>> code iterator for success result mode. >>>> * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use >>>> the corresponding new insn generators. >>>> >>>> Testing: arm-none-eabi cross-compiler built successfully for ARMv8-M >>>> Mainline and Baseline without the lack of destination mode warning in >>>> sync.md. Testsuite show no regression. >>>> >>> >>> Thanks for fixing these warnings. >>> The code looks ok to me but >>> I'd like to make sure that the rest of the arm atomic targets are not adversely >>> affected, >>> so please also do a test run for ARMv7-A and ARMv8-A targets. >>> Also, a bootstrap is required as always. >> >> Hi Kyrill, >> >> Bootstrapped and ran the testsuite for both ARMv7-A and ARMv8-A in both ARM >> and Thumb mode without any regression. I've also verified that a number of >> atomic related testcases [1][2] get the same code generation for ARMv7-A in >> ARM and Thumb mode as well as ARMv8-M Baseline. >> >> [1] For ARMv7-A ARM and Thumb mode, the following testcases were considered: >> >> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-fence.c >> gcc/testsuite/gcc.dg/atomic-flag.c >> gcc/testsuite/gcc.dg/atomic-generic.c >> gcc/testsuite/gcc.dg/atomic-generic-aux.c >> gcc/testsuite/gcc.dg/atomic-invalid-2.c >> gcc/testsuite/gcc.dg/atomic-load-1.c >> gcc/testsuite/gcc.dg/atomic-load-2.c >> gcc/testsuite/gcc.dg/atomic-load-3.c >> gcc/testsuite/gcc.dg/atomic-lockfree.c >> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c >> gcc/testsuite/gcc.dg/atomic-noinline.c >> gcc/testsuite/gcc.dg/atomic-noinline-aux.c >> gcc/testsuite/gcc.dg/atomic-op-1.c >> gcc/testsuite/gcc.dg/atomic-op-2.c >> gcc/testsuite/gcc.dg/atomic-op-3.c >> gcc/testsuite/gcc.dg/atomic-op-6.c >> gcc/testsuite/gcc.dg/atomic-store-1.c >> gcc/testsuite/gcc.dg/atomic-store-2.c >> gcc/testsuite/gcc.dg/atomic-store-3.c >> gcc/testsuite/g++.dg/ext/atomic-1.C >> gcc/testsuite/g++.dg/ext/atomic-2.C >> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-char-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-int-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-release-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c >> gcc/testsuite/gcc.target/arm/atomic-op-short-1.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c >> gcc/testsuite/gcc.target/arm/sync-1.c >> gcc/testsuite/gcc.target/arm/synchronize.c >> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c >> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc >> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc >> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc >> >> [2] For ARMv8-M Baseline, the following testcases were considered: >> >> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-fence.c >> gcc/testsuite/gcc.dg/atomic-flag.c >> gcc/testsuite/gcc.dg/atomic-generic.c >> gcc/testsuite/gcc.dg/atomic-generic-aux.c >> gcc/testsuite/gcc.dg/atomic-invalid-2.c >> gcc/testsuite/gcc.dg/atomic-load-1.c >> gcc/testsuite/gcc.dg/atomic-load-2.c >> gcc/testsuite/gcc.dg/atomic-load-3.c >> gcc/testsuite/gcc.dg/atomic-lockfree.c >> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c >> gcc/testsuite/gcc.dg/atomic-noinline.c >> gcc/testsuite/gcc.dg/atomic-noinline-aux.c >> gcc/testsuite/gcc.dg/atomic-op-1.c >> gcc/testsuite/gcc.dg/atomic-op-2.c >> gcc/testsuite/gcc.dg/atomic-op-3.c >> gcc/testsuite/gcc.dg/atomic-op-6.c >> gcc/testsuite/gcc.dg/atomic-store-1.c >> gcc/testsuite/gcc.dg/atomic-store-2.c >> gcc/testsuite/gcc.dg/atomic-store-3.c >> gcc/testsuite/g++.dg/ext/atomic-1.C >> gcc/testsuite/g++.dg/ext/atomic-2.C >> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-char-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-int-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-release-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c >> gcc/testsuite/gcc.target/arm/atomic-op-short-3.c >> gcc/testsuite/gcc.target/arm/sync-1.c >> gcc/testsuite/gcc.target/arm/synchronize.c >> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c >> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc >> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc >> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc >> >>> >>> Ok with that testing. >> >> Just to make sure, canyou confirm again that you're Ok for this to be commited >> in trunk with that amount of testing now that GCC 7.1 is released? >> > > Thanks for the thorough testing, this is ok for trunk. > > Kyrill > >> Best regards, >> >> Thomas > --------------6F5E99133647E31965D1D707 Content-Type: text/x-patch; name="fix_atomic_compare_swap_success_mode.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="fix_atomic_compare_swap_success_mode.patch" Content-length: 5230 diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm index 560df13d119d740beb56d2b9f2cd33be40a41db9..8cde4f43ee65184c316ab4c7e5b78c5bb0c6e7bb 100644 --- a/gcc/ChangeLog.arm +++ b/gcc/ChangeLog.arm @@ -1,3 +1,17 @@ +2017-06-01 Thomas Preud'homme + + Backport from mainline + 2017-05-03 Thomas Preud'homme + + * config/arm/iterators.md (CCSI): New mode iterator. + (arch): New mode attribute. + * config/arm/sync.md (atomic_compare_and_swap_1): Rename into ... + (atomic_compare_and_swap_1): This and ... + (atomic_compare_and_swap_1): This. Use CCSI + code iterator for success result mode. + * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use + the corresponding new insn generators. + 2017-05-31 Prakhar Bahuguna Backport from mainline diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7b7558fc4e1e797e099a8233c52e369aa7af0dad..635468dd071e09af5bb8139f6566ac51e232db6b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -29049,17 +29049,32 @@ arm_expand_compare_and_swap (rtx operands[]) gcc_unreachable (); } - switch (mode) + if (TARGET_THUMB1) { - case QImode: gen = gen_atomic_compare_and_swapqi_1; break; - case HImode: gen = gen_atomic_compare_and_swaphi_1; break; - case SImode: gen = gen_atomic_compare_and_swapsi_1; break; - case DImode: gen = gen_atomic_compare_and_swapdi_1; break; - default: - gcc_unreachable (); + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swapt1qi_1; break; + case HImode: gen = gen_atomic_compare_and_swapt1hi_1; break; + case SImode: gen = gen_atomic_compare_and_swapt1si_1; break; + case DImode: gen = gen_atomic_compare_and_swapt1di_1; break; + default: + gcc_unreachable (); + } + } + else + { + switch (mode) + { + case QImode: gen = gen_atomic_compare_and_swap32qi_1; break; + case HImode: gen = gen_atomic_compare_and_swap32hi_1; break; + case SImode: gen = gen_atomic_compare_and_swap32si_1; break; + case DImode: gen = gen_atomic_compare_and_swap32di_1; break; + default: + gcc_unreachable (); + } } - bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM); + bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CC_Zmode, CC_REGNUM); emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f)); if (mode == QImode || mode == HImode) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 572affc3fdc158606340a7b4926f437fb9fddf7d..c1d462cdf4cd7dbfe6518ad6f3cf41e84009127d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -45,6 +45,9 @@ ;; A list of the 32bit and 64bit integer modes (define_mode_iterator SIDI [SI DI]) +;; A list of atomic compare and swap success return modes +(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) + ;; A list of modes which the VFP unit can handle (define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) @@ -370,6 +373,10 @@ ;; Mode attributes ;;---------------------------------------------------------------------------- +;; Determine name of atomic compare and swap from success result mode. This +;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. +(define_mode_attr arch [(CC_Z "32") (SI "t1")]) + ;; Determine element size suffix from vector mode. (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 64a12d762112a1e8eb3907d353071187765153a2..511bb4364c8a5a373a3067a23e812ca3878c1b25 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -191,9 +191,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory @@ -223,9 +223,9 @@ ;; Constraints of this pattern must be at least as strict as those of the ;; cbranchsi operations in thumb1.md and aim to be as permissive. -(define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out - (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) +(define_insn_and_split "atomic_compare_and_swap_1" + [(set (match_operand:CCSI 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out + (unspec_volatile:CCSI [(const_int 0)] VUNSPEC_ATOMIC_CAS)) (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2) --------------6F5E99133647E31965D1D707--