From: 钟居哲 <juzhe.zhong@rivai.ai>
To: kito.cheng <kito.cheng@sifive.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
kito.cheng <kito.cheng@gmail.com>, palmer <palmer@dabbelt.com>,
"Jeff Law" <jeffreyalaw@gmail.com>
Cc: kito.cheng <kito.cheng@sifive.com>
Subject: Re: [wwwdocs] gcc-13: Add release note for RISC-V
Date: Wed, 19 Apr 2023 22:38:50 +0800 [thread overview]
Message-ID: <3549B323B75A61C6+202304192238502871830@rivai.ai> (raw)
In-Reply-To: <20230419135351.98376-1-kito.cheng@sifive.com>
[-- Attachment #1: Type: text/plain, Size: 2035 bytes --]
LGTM。
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-04-19 21:53
To: gcc-patches; kito.cheng; palmer; juzhe.zhong; jeffreyalaw
CC: Kito Cheng
Subject: [wwwdocs] gcc-13: Add release note for RISC-V
---
htdocs/gcc-13/changes.html | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,9 +636,32 @@ a work-in-progress.</p>
<h3 id="riscv">RISC-V</h3>
<ul>
- <li>New ISA extension support for zawrs.</li>
+ <li>Supports vector intrinsics as specified in <a
+ href="https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v0.11.x">
+ version 0.11 of the RISC-V vector intrinsic specification</a>,
+ thanks Ju-Zhe Zhong from <a href="https://rivai-ic.com.cn/">RiVAI</a>
+ for contributing most of implementation.
+ </li>
<li>Support for the following vendor extensions has been added:
<ul>
+ <li>Zawrs</li>
+ <li>Zicbom</li>
+ <li>Zicboz</li>
+ <li>Zicbop</li>
+ <li>Zfh</li>
+ <li>Zfhmin</li>
+ <li>Zmmul</li>
+ <li>Zdinx</li>
+ <li>Zfinx</li>
+ <li>Zhinx</li>
+ <li>Zhinxmin</li>
+ <li>Zksh</li>
+ <li>Zksed</li>
+ <li>Zknd</li>
+ <li>Zkne</li>
+ <li>Zbkb</li>
+ <li>Zbkc</li>
+ <li>Zbkx</li>
<li>XTheadBa</li>
<li>XTheadBb</li>
<li>XTheadBs</li>
@@ -657,8 +680,14 @@ a work-in-progress.</p>
option (GCC identifiers in parentheses).
<ul>
<li>T-Head's XuanTie C906 (<code>thead-c906</code>).</li>
+ <li>Ventana's VT1 (<code>ventana-vt1</code>).</li>
</ul>
</li>
+ <li>Improves the multi-lib selection mechanism for the bare-metal toolchain
+ (riscv*-elf*). GCC will now automatically select the best-fit multi-lib
+ candidate instead of requiring all possible reuse rules to be listed at
+ build time.
+ </li>
</ul>
<!-- <h3 id="rx">RX</h3> -->
--
2.39.2
next prev parent reply other threads:[~2023-04-19 14:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 13:53 Kito Cheng
2023-04-19 14:38 ` 钟居哲 [this message]
2023-04-19 14:42 ` Palmer Dabbelt
2023-04-19 15:08 ` Kito Cheng
2023-04-20 6:22 jiawei
2023-04-20 6:35 ` Kito Cheng
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