From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id DAA18385696F for ; Thu, 7 Jul 2022 08:30:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DAA18385696F Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2677Dh4Y031252; Thu, 7 Jul 2022 08:30:59 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3h5twf9xch-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Jul 2022 08:30:58 +0000 Received: from m0127361.ppops.net (m0127361.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 26780qfc024684; Thu, 7 Jul 2022 08:30:58 GMT Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3h5twf9xbw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Jul 2022 08:30:58 +0000 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2678Lq5g023407; Thu, 7 Jul 2022 08:30:56 GMT Received: from b06avi18878370.portsmouth.uk.ibm.com (b06avi18878370.portsmouth.uk.ibm.com [9.149.26.194]) by ppma06ams.nl.ibm.com with ESMTP id 3h4usd2964-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Jul 2022 08:30:56 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2678V2Vi32112920 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Jul 2022 08:31:02 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E29052051; Thu, 7 Jul 2022 08:30:53 +0000 (GMT) Received: from [9.197.235.122] (unknown [9.197.235.122]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id D54645204E; Thu, 7 Jul 2022 08:30:51 +0000 (GMT) Message-ID: <368de06c-f6d6-e759-0f91-5df170687346@linux.ibm.com> Date: Thu, 7 Jul 2022 16:30:50 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner From: HAO CHEN GUI Subject: [PATCH v2] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453] Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: rGRVUr-TGKS1j0RIGkbbBSqnnRcedk9H X-Proofpoint-GUID: 74zPE8Y9gZYadu-CQJBsbxcSM1cpwJR8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-07_06,2022-06-28_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 mlxscore=0 spamscore=0 priorityscore=1501 adultscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207070031 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jul 2022 08:31:01 -0000 Hi, This patch modifies the combine pattern after recog fails. With a helper - change_pseudo_and_mask, it converts a single pseudo to the pseudo AND with a mask when the outer operator is IOR/XOR/PLUS and inner operator is ASHIFT or AND. The conversion helps pattern to match rotate and mask insn on some targets. For test case rlwimi-2.c, current trunk fails on "scan-assembler-times (?n)^\\s+[a-z]". It reports 21305 times. So my patch reduces the total number of insns from 21305 to 21279. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2022-07-07 Haochen Gui gcc/ PR target/93453 * combine.cc (change_pseudo_and_mask): New. (recog_for_combine): If recog fails, try again with the pattern modified by change_pseudo_and_mask. * config/rs6000/rs6000.md (plus_ior_xor): Removed. (anonymous split pattern for plus_ior_xor): Removed. gcc/testsuite/ PR target/93453 * gcc.target/powerpc/20050603-3.c: Modify dump check conditions. * gcc.target/powerpc/rlwimi-2.c: Likewise. * gcc.target/powerpc/pr93453-2.c: New. patch.diff diff --git a/gcc/combine.cc b/gcc/combine.cc index a5fabf397f7..3cd7b2b652b 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -11599,6 +11599,47 @@ change_zero_ext (rtx pat) return changed; } +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is + ASHIFT/AND, convert a pseudo to psuedo AND with a mask if its nonzero_bits + is less than its mode mask. The nonzero_bits in other pass doesn't return + the same value as it does in combine pass. */ +static bool +change_pseudo_and_mask (rtx pat) +{ + rtx src = SET_SRC (pat); + if ((GET_CODE (src) == IOR + || GET_CODE (src) == XOR + || GET_CODE (src) == PLUS) + && (((GET_CODE (XEXP (src, 0)) == ASHIFT + || GET_CODE (XEXP (src, 0)) == AND) + && REG_P (XEXP (src, 1))))) + { + rtx *reg = &XEXP (SET_SRC (pat), 1); + machine_mode mode = GET_MODE (*reg); + unsigned HOST_WIDE_INT nonzero = nonzero_bits (*reg, mode); + if (nonzero < GET_MODE_MASK (mode)) + { + int shift; + + if (GET_CODE (XEXP (src, 0)) == ASHIFT) + shift = INTVAL (XEXP (XEXP (src, 0), 1)); + else + shift = ctz_hwi (INTVAL (XEXP (XEXP (src, 0), 1))); + + if (shift > 0 + && ((HOST_WIDE_INT_1U << shift) - 1) >= nonzero) + { + unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << shift) - 1; + rtx x = gen_rtx_AND (mode, *reg, GEN_INT (mask)); + SUBST (*reg, x); + maybe_swap_commutative_operands (SET_SRC (pat)); + return true; + } + } + } + return false; +} + /* Like recog, but we receive the address of a pointer to a new pattern. We try to match the rtx that the pointer points to. If that fails, we may try to modify or replace the pattern, @@ -11646,7 +11687,10 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) } } else - changed = change_zero_ext (pat); + { + changed = change_pseudo_and_mask (pat); + changed |= change_zero_ext (pat); + } } else if (GET_CODE (pat) == PARALLEL) { diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1367a2cb779..2bd6bd5f908 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4207,24 +4207,6 @@ (define_insn_and_split "*rotl3_insert_3_" (ior:GPR (and:GPR (match_dup 3) (match_dup 4)) (ashift:GPR (match_dup 1) (match_dup 2))))]) -(define_code_iterator plus_ior_xor [plus ior xor]) - -(define_split - [(set (match_operand:GPR 0 "gpc_reg_operand") - (plus_ior_xor:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand") - (match_operand:SI 2 "const_int_operand")) - (match_operand:GPR 3 "gpc_reg_operand")))] - "nonzero_bits (operands[3], mode) - < HOST_WIDE_INT_1U << INTVAL (operands[2])" - [(set (match_dup 0) - (ior:GPR (and:GPR (match_dup 3) - (match_dup 4)) - (ashift:GPR (match_dup 1) - (match_dup 2))))] -{ - operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1); -}) - (define_insn "*rotlsi3_insert_4" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0") diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc/testsuite/gcc.target/powerpc/20050603-3.c index 4017d34f429..e628be11532 100644 --- a/gcc/testsuite/gcc.target/powerpc/20050603-3.c +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c @@ -12,7 +12,7 @@ void rotins (unsigned int x) b.y = (x<<12) | (x>>20); } -/* { dg-final { scan-assembler-not {\mrlwinm} } } */ +/* { dg-final { scan-assembler-not {\mrlwinm} { target ilp32 } } } */ /* { dg-final { scan-assembler-not {\mrldic} } } */ /* { dg-final { scan-assembler-not {\mrot[lr]} } } */ /* { dg-final { scan-assembler-not {\ms[lr][wd]} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr93453-2.c b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c new file mode 100644 index 00000000000..34b7834af8d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long foo (char a, long b) +{ + long c = a; + c = c | (b << 12); + return c; +} + +long bar (long b, char a) +{ + long c = a; + long m = -4096; + c = c | (b & m); + return c; +} + +/* { dg-final { scan-assembler-times {\mrlwimi\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c index bafa371db73..ffb5f9e450f 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c @@ -2,14 +2,14 @@ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 21279 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */