From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 51186 invoked by alias); 11 Apr 2017 14:47:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 50845 invoked by uid 89); 11 Apr 2017 14:47:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 11 Apr 2017 14:47:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4DCA7CFC; Tue, 11 Apr 2017 07:47:06 -0700 (PDT) Received: from [10.2.206.201] (e105545-lin.cambridge.arm.com [10.2.206.201]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 692D83F23B; Tue, 11 Apr 2017 07:47:05 -0700 (PDT) Subject: Re: [PATCH, GCC/ARM, gcc-5-branch] Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R To: Thomas Preudhomme , Ramana Radhakrishnan References: <66eefa85-d2c0-4b74-fd01-db137502e61a@foss.arm.com> Cc: Kyrill Tkachov , Richard Earnshaw , "gcc-patches@gcc.gnu.org" From: Ramana Radhakrishnan Message-ID: <36a709a2-17ab-dc2b-93df-a4076c3c02f1@foss.arm.com> Date: Tue, 11 Apr 2017 14:47:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <66eefa85-d2c0-4b74-fd01-db137502e61a@foss.arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2017-04/txt/msg00527.txt.bz2 On 10/04/17 13:12, Thomas Preudhomme wrote: > Hi, > > Currently GCC is happy to use LDRD to perform a 64bit load on ARMv7-R, > as shown by the testcase on this patch. However, LDRD is only atomic > when LPAE extensions is available, which they are not for ARMv7-R. This > commit solve the issue by introducing a new feature bit to distinguish > LPAE extensions instead of deducing it from div instruction > availability. > > ChangeLog entries are as follow: > > *** gcc/ChangeLog *** > > 2017-03-22 Thomas Preud'homme > > PR target/80082 > * config/arm/arm-protos.h (FL_LPAE): Define macro. > (FL_FOR_ARCH7VE): Add FL_LPAE. > (arm_arch_lpae): Declare extern. > * config/arm/arm.c (arm_arch_lpae): Declare. > (arm_option_override): Define arm_arch_lpae. > * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of > arm_arch_lpae. > > *** gcc/testsuite/ChangeLog *** > > 2017-03-22 Thomas Preud'homme > > PR target/80082 > * gcc.target/arm/atomic_loaddi_10.c: New testcase. > * gcc.target/arm/atomic_loaddi_11.c: Likewise. > > Is this ok for gcc-5-branch? OK. Ramana > > Best regards, > > Thomas > > On 06/04/17 14:05, Ramana Radhakrishnan wrote: >> On Mon, Mar 27, 2017 at 12:15 PM, Thomas Preudhomme >> wrote: >>> Hi, >>> >>> Currently GCC is happy to use LDRD to perform a 64bit load on ARMv7-R, >>> as shown by the testcase on this patch. However, LDRD is only atomic >>> when LPAE extensions is available, which they are not for ARMv7-R. This >>> commit solve the issue by introducing a new feature bit to distinguish >>> LPAE extensions instead of deducing it from div instruction >>> availability. >> >> >> Ok but with the testsuite fix that I just approved, please also fix >> in gcc-5 branch. >> >> Thanks, >> Ramana >> >>> >>> ChangeLog entries are as follow: >>> >>> *** gcc/ChangeLog *** >>> >>> 2017-03-22 Thomas Preud'homme >>> >>> PR target/80082 >>> * config/arm/arm-protos.h (FL_LPAE): Define macro. >>> (FL_FOR_ARCH7VE): Add FL_LPAE. >>> (arm_arch_lpae): Declare extern. >>> * config/arm/arm.c (arm_arch_lpae): Declare. >>> (arm_option_override): Define arm_arch_lpae. >>> * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of >>> arm_arch_lpae. >>> >>> *** gcc/testsuite/ChangeLog *** >>> >>> 2017-03-22 Thomas Preud'homme >>> >>> PR target/80082 >>> * gcc.target/arm/atomic_loaddi_10.c: New testcase. >>> * gcc.target/arm/atomic_loaddi_11.c: Likewise. >>> >>> >>> Testing: bootstrapped for -march=armv7ve and testsuite shows no >>> regression. >>> >>> Is this ok for gcc-6-branch? >>> >>> Best regards, >>> >>> Thomas