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Thu, 30 Jan 2020 14:42:12 +0000 From: Stam Markianos-Wright Subject: Re: [PING][PATCH][GCC][ARM] Arm generates out of range conditional branches in Thumb2 (PR91816) To: Kyrill Tkachov , "gcc-patches@gcc.gnu.org" Cc: "nickc@redhat.com" , Ramana Radhakrishnan , Richard Earnshaw References: <687026c0-05ac-21bc-3b7f-16d138c49134@arm.com> <9e889eb7-5c5f-3aad-5801-8e972c97856a@arm.com> <80f43481-413d-25cf-2c7e-4375d56eb2ac@foss.arm.com> <2703fb2d-6ec5-7eb9-cd97-781c1f7b852e@arm.com> <4978a614-d413-3fc4-05c9-d8c0ad618c08@foss.arm.com> Message-ID: <36c9c580-2b73-c780-656b-5bce51af464a@arm.com> Date: Thu, 30 Jan 2020 14:55:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 In-Reply-To: <4978a614-d413-3fc4-05c9-d8c0ad618c08@foss.arm.com> Content-Type: multipart/mixed; boundary="------------14A2F4EBC85C202091358A05" MIME-Version: 1.0 Received: from [10.2.74.61] (217.140.106.49) by CWLP123CA0102.GBRP123.PROD.OUTLOOK.COM (2603:10a6:401:5f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.27 via Frontend Transport; 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Return-Path: Stam.Markianos-Wright@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT052.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 444d7c12-8ca6-4e29-6847-08d7a592979c X-IsSubscribed: yes X-SW-Source: 2020-01/txt/msg02011.txt.bz2 --------------14A2F4EBC85C202091358A05 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-length: 1667 On 1/28/20 10:35 AM, Kyrill Tkachov wrote: > Hi Stam, > > On 1/8/20 3:18 PM, Stam Markianos-Wright wrote: >> >> On 12/10/19 5:03 PM, Kyrill Tkachov wrote: >>> Hi Stam, >>> >>> On 11/15/19 5:26 PM, Stam Markianos-Wright wrote: >>>> Pinging with more correct maintainers this time :) >>>> >>>> Also would need to backport to gcc7,8,9, but need to get this approved >>>> first! >>>> >>> Sorry for the delay. >> Same here now! Sorry totally forget about this in the lead up to Xmas! >> >> Done the changes marked below and also removed the unnecessary extra #defines >> from the test. > > > This is ok with a nit on the testcase... > > > diff --git a/gcc/testsuite/gcc.target/arm/pr91816.c > b/gcc/testsuite/gcc.target/arm/pr91816.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..757c897e9c0db32709227b3fdf1b4a8033428232 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr91816.c > @@ -0,0 +1,61 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=armv7-a -mthumb -mfpu=vfpv3-d16" }  */ > +int printf(const char *, ...); > + > > I think this needs a couple of effective target checks like arm_hard_vfp_ok and > arm_thumb2_ok. See other tests in gcc.target/arm that add -mthumb to the options. Hmm, looking back at this now, is there any reason why it can't just be: /* { dg-do compile } */ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-additional-options "-mthumb" } */ were we don't override the march or fpu options at all, but just use `require-effective-target arm_thumb2_ok` to make sure that thumb2 is supported? The attached new diff does just that. Cheers :) Stam. > > Thanks, > Kyrill > --------------14A2F4EBC85C202091358A05 Content-Type: text/plain; charset=UTF-8; name="1" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="1" Content-length: 11070 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL2FybS1wcm90b3MuaCBiL2dj Yy9jb25maWcvYXJtL2FybS1wcm90b3MuaAppbmRleCA3YzRiMTAwMzg0NC4u ODg5NWJlY2M2MzkgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYXJtL2FybS1w cm90b3MuaAorKysgYi9nY2MvY29uZmlnL2FybS9hcm0tcHJvdG9zLmgKQEAg LTU3Niw0ICs1NzYsNiBAQCB2b2lkIGFybV9wYXJzZV9vcHRpb25fZmVhdHVy ZXMgKHNiaXRtYXAsIGNvbnN0IGNwdV9hcmNoX29wdGlvbiAqLAogCiB2b2lk IGFybV9pbml0aWFsaXplX2lzYSAoc2JpdG1hcCwgY29uc3QgZW51bSBpc2Ff ZmVhdHVyZSAqKTsKIAorY29uc3QgY2hhciAqIGFybV9nZW5fZmFyX2JyYW5j aCAocnR4ICosIGludCwgY29uc3QgY2hhciAqICwgY29uc3QgY2hhciAqKTsK KwogI2VuZGlmIC8qICEgR0NDX0FSTV9QUk9UT1NfSCAqLwpkaWZmIC0tZ2l0 IGEvZ2NjL2NvbmZpZy9hcm0vYXJtLmMgYi9nY2MvY29uZmlnL2FybS9hcm0u YwppbmRleCAwNzIzMWQ3MjJiOS4uZWU1ZGUxNjlmM2UgMTAwNjQ0Ci0tLSBh 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