From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 8CC913858D28; Fri, 1 Apr 2022 11:39:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8CC913858D28 Received: from [IPv6:240e:358:11c6:7500:f76e:267c:b511:b6a3] (unknown [IPv6:240e:358:11c6:7500:f76e:267c:b511:b6a3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id 96769663B2; Fri, 1 Apr 2022 07:39:05 -0400 (EDT) Message-ID: <36d825b98e0f18f6fff182473c3a4fff4809f722.camel@mengyan1223.wang> Subject: [PATCH v2] mips: Emit psabi diagnostic for return values affected by C++ zero-width bit-field ABI change [PR 102024] From: Xi Ruoyao To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org, Jakub Jelinek , Richard Sandiford , YunQiang Su Date: Fri, 01 Apr 2022 19:38:59 +0800 In-Reply-To: References: <03bbbd29325ec7f76809ef63ef8f92f930442a18.camel@mengyan1223.wang> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-3039.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Apr 2022 11:39:14 -0000 v1 -> v2: * "int has_zero_width_bf" -> "bool has_cxx_zero_width_bf". "int" to "bool" because the value is 0/1 only. Add "cxx" because it only indicates C++ zero-width bit-fields (not those bit-fields from C). * Coding style fix. * Rewrite mips_return_in_msb so mips_fpr_return_fields is not called unnecessarily. * "retcon" -> "change". gcc/ PR target/102024 * mips.cc (mips_fpr_return_fields): Detect C++ zero-width bit-fields and set up an indicator. (mips_return_in_msb): Adapt for mips_fpr_return_fields change. (mips_function_value_1): Diagnose when the presense of a C++ zero-width bit-field changes function returning in GCC 12. gcc/testsuite/ PR target/102024 * g++.target/mips/mips.exp: New test supporting file. * g++.target/mips/pr102024-1.C: New test. --- gcc/config/mips/mips.cc | 58 ++++++++++++++++++++---- gcc/testsuite/g++.target/mips/mips.exp | 34 ++++++++++++++ gcc/testsuite/g++.target/mips/pr102024.C | 20 ++++++++ 3 files changed, 104 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/g++.target/mips/mips.exp create mode 100644 gcc/testsuite/g++.target/mips/pr102024.C diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 91e1e964f94..83860b5d4b7 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -6274,10 +6274,17 @@ mips_callee_copies (cumulative_args_t, const functi= on_arg_info &arg) =20 For n32 & n64, a structure with one or two fields is returned in floating-point registers as long as every field has a floating-point - type. */ + type. + + The C++ FE used to remove zero-width bit-fields in GCC 11 and earlier. + To make a proper diagnostic, this function will set + HAS_CXX_ZERO_WIDTH_BF to true once a C++ zero-width bit-field shows up, + and then ignore it. Then the caller can determine if this zero-width + bit-field will make a difference and emit a -Wpsabi inform. */ =20 static int -mips_fpr_return_fields (const_tree valtype, tree *fields) +mips_fpr_return_fields (const_tree valtype, tree *fields, + bool *has_cxx_zero_width_bf) { tree field; int i; @@ -6294,6 +6301,12 @@ mips_fpr_return_fields (const_tree valtype, tree *fi= elds) if (TREE_CODE (field) !=3D FIELD_DECL) continue; =20 + if (DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD (field)) + { + *has_cxx_zero_width_bf =3D true; + continue; + } + if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) return 0; =20 @@ -6318,12 +6331,14 @@ mips_fpr_return_fields (const_tree valtype, tree *f= ields) static bool mips_return_in_msb (const_tree valtype) { - tree fields[2]; + if (!TARGET_NEWABI || !TARGET_BIG_ENDIAN || !AGGREGATE_TYPE_P (valtype)) + return false; =20 - return (TARGET_NEWABI - && TARGET_BIG_ENDIAN - && AGGREGATE_TYPE_P (valtype) - && mips_fpr_return_fields (valtype, fields) =3D=3D 0); + tree fields[2]; + bool has_cxx_zero_width_bf =3D false; + return (mips_fpr_return_fields (valtype, fields, + &has_cxx_zero_width_bf) =3D=3D 0 + || has_cxx_zero_width_bf); } =20 /* Return true if the function return value MODE will get returned in a @@ -6418,8 +6433,35 @@ mips_function_value_1 (const_tree valtype, const_tre= e fn_decl_or_type, return values, promote the mode here too. */ mode =3D promote_function_mode (valtype, mode, &unsigned_p, func, 1)= ; =20 + bool has_cxx_zero_width_bf =3D false; + int use_fpr =3D mips_fpr_return_fields (valtype, fields, + &has_cxx_zero_width_bf); + if (TARGET_HARD_FLOAT + && warn_psabi + && has_cxx_zero_width_bf + && use_fpr !=3D 0) + { + static unsigned last_reported_type_uid; + unsigned uid =3D TYPE_UID (TYPE_MAIN_VARIANT (valtype)); + if (uid !=3D last_reported_type_uid) + { + static const char *url + =3D CHANGES_ROOT_URL + "gcc-12/changes.html#zero_width_bitfields"; + inform (input_location, + "the ABI for returning a value containing " + "zero-width bit-fields but otherwise an aggregate " + "with only one or two floating-point fields was " + "changed in GCC %{12.1%}", url); + last_reported_type_uid =3D uid; + } + } + + if (has_cxx_zero_width_bf) + use_fpr =3D 0; + /* Handle structures whose fields are returned in $f0/$f2. */ - switch (mips_fpr_return_fields (valtype, fields)) + switch (use_fpr) { case 1: return mips_return_fpr_single (mode, diff --git a/gcc/testsuite/g++.target/mips/mips.exp b/gcc/testsuite/g++.tar= get/mips/mips.exp new file mode 100644 index 00000000000..9fa7e771b4d --- /dev/null +++ b/gcc/testsuite/g++.target/mips/mips.exp @@ -0,0 +1,34 @@ +# Copyright (C) 2019-2022 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a MIPS target. +if ![istarget mips*-*-*] then { + return +} + +# Load support procs. +load_lib g++-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/g++.target/mips/pr102024.C b/gcc/testsuite/g++.t= arget/mips/pr102024.C new file mode 100644 index 00000000000..331e6ca70e6 --- /dev/null +++ b/gcc/testsuite/g++.target/mips/pr102024.C @@ -0,0 +1,20 @@ +// PR target/102024 +// { dg-do compile } +// { dg-options "-O2 -mabi=3D64 -mhard-float" } +// { dg-final { scan-assembler-not "\\\$f0" } } + +struct foo +{ + double a; + int : 0; + double b; +}; + +struct foo +make_foo(void) // { dg-message "the ABI for returning a value containing z= ero-width bit-fields but otherwise an aggregate with only one or two floati= ng-point fields was changed in GCC 12.1" } +{ + struct foo ret; + ret.a =3D 114; + ret.b =3D 514; + return ret; +} --=20 2.35.1