From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 4AC0D38582BF for ; Tue, 9 Jan 2024 22:35:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4AC0D38582BF Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4AC0D38582BF Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704839730; cv=none; b=IWJ8p3QkN6FudicSaSBe4OIAxZ3FrazXMukPutgx3X9Fd44jT+oc/TXiG81b3z+tOWDpVEDMUhnxTrx8Va5g/wo+YYOVFLuVtkeOCEO3V7e/ek07g4lwNEFRxUz3HCVLQDXklXPIWb7iyvWs1V1suAxsFCKk0E6ew4hZYiQJYTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704839730; c=relaxed/simple; bh=2B20scSxzns2vtnjVn2tgR79kAx2kneKkdZ8HPNaz4U=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=OBdII5P9p9j/xhj6C2secVog3NHJCXeOH2rLJH9JgLtw4hc5yvX8PvQfDS1V6E8OQCwFoA6QbSNW5ZJ2v4zcEwhHY+0KBi0UpA/qFKDT69vbKlEYSzNDryF35t7RSRh2Wtp5gnisdz3hzgc4FavL65wAXxZodhTVjmYoFCb1jZc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 409KvFTu005120; Tue, 9 Jan 2024 22:35:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=Gduu9+uTTxsqgreufR1u+ZrqK0PHShZsaMVbAcOQ4Z0=; b=h6JoZtpVl/cApd7Av4LEVszMzJlJalgXYd/taXhsL0gpmV23k2SymSCbI/kDUcJbsUP1 9KcTTCw2RxVslf2CTaMzMNxmG7G7ASkCfN+Lcqc0JUnxkvlvMqg6Cn5VbCT1FToJs0BJ y5C9nmTtOejIz9nQs1+mKGv2f0PEq+ZLDlvSg9EOd0a+U0UpXeqT109vWHu6ZCQV3+P4 0zo1oxQpllOrlIoQ7ZKP/YnlwJUV7Ru97TiOBph1lybnnTnpisLBKm6724N08+yjA8Up jHCX0g1ysTjkkfgNKHjuq4nTCVV1myyTRz4hnl5TrIo8/lSQ//LiYMLYPeyN7Uwlh49G EQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3vhdmp9xa4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jan 2024 22:35:26 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 409MFDU2028158; Tue, 9 Jan 2024 22:35:26 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3vhdmp9x9t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jan 2024 22:35:26 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 409JiNvi004388; Tue, 9 Jan 2024 22:35:25 GMT Received: from smtprelay06.dal12v.mail.ibm.com ([172.16.1.8]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3vfjpksf0j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jan 2024 22:35:25 +0000 Received: from smtpav03.wdc07v.mail.ibm.com (smtpav03.wdc07v.mail.ibm.com [10.39.53.230]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 409MZNu720120154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 9 Jan 2024 22:35:24 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CCE7C5805A; Tue, 9 Jan 2024 22:35:23 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 31BDF58054; Tue, 9 Jan 2024 22:35:23 +0000 (GMT) Received: from [9.61.54.76] (unknown [9.61.54.76]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 9 Jan 2024 22:35:23 +0000 (GMT) Message-ID: <36dced66-4511-4d3a-a780-d8bcfcc4b64e@linux.ibm.com> Date: Tue, 9 Jan 2024 16:35:22 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PR target/112886, Add %S to print_operand for vector pair support Content-Language: en-US To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn References: From: Peter Bergner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 8r2CEIkw2bp1rtdoQocpH6XjJ06JrPvs X-Proofpoint-GUID: pBJOYMBY7eHgOph3ErehOyD-aModEzXU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-09_11,2024-01-09_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=935 priorityscore=1501 malwarescore=0 clxscore=1011 spamscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401090180 X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 1/5/24 4:18 PM, Michael Meissner wrote: > @@ -14504,13 +14504,17 @@ print_operand (FILE *file, rtx x, int code) > print_operand (file, x, 0); > return; > > + case 'S': > case 'x': > - /* X is a FPR or Altivec register used in a VSX context. */ > + /* X is a FPR or Altivec register used in a VSX context. %x prints > + the VSX register number, %S prints the 2nd register number for > + vector pair, decimal 128-bit floating and IBM 128-bit binary floating > + values. */ > if (!REG_P (x) || !VSX_REGNO_P (REGNO (x))) > - output_operand_lossage ("invalid %%x value"); > + output_operand_lossage ("invalid %%%c value", (code == 'S' ? 'S' : 'x')); > else > { > - int reg = REGNO (x); > + int reg = REGNO (x) + (code == 'S' ? 1 : 0); > int vsx_reg = (FP_REGNO_P (reg) > ? reg - 32 > : reg - FIRST_ALTIVEC_REGNO + 32); The above looks good to me. However: > + : "=v" (*p) > + : "v" (*q), "v" (*r)); These really should use "wa" rather than "v", since these are VSX instructions... or did you use those to ensure you got Altivec registers numbers assigned? > +/* { dg-final { scan-assembler-times {\mxvadddp (3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3])\M} 2 } } */ ...and this is really ugly and hard to read/understand. Can't we use register variables to make it simpler? Something like the following which tests having both FPR and Altivec reg numbers assigned? ... void test (__vector_pair *ptr) { register __vector_pair p asm ("vs10"); register __vector_pair q asm ("vs42"); register __vector_pair r asm ("vs44"); q = ptr[1]; r = ptr[2]; __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %S0,%S1,%S2" : "=wa" (p) : "wa" (q), "wa" (r)); ptr[2] = p; } /* { dg-final { scan-assembler-times {\mxvadddp 10,42,44\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvadddp 11,43,45\M} 1 } } */ ... Peter