From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: [PATCH v2] RISC-V: Fix Zicond ICE on large constants
Date: Tue, 5 Sep 2023 12:08:53 +0000 [thread overview]
Message-ID: <37a03341f16da30b83bec1f4ef51dce4e6f25264.1693915537.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Large constant cons and/or alt will trigger ICEs building GCC target
libraries (libgomp and libatomic) when the 'Zicond' extension is enabled.
For instance, zicond-ice-2.c (new test case in this commit) will cause
an ICE when SOME_NUMBER is 0x1000 or larger. While opposite numbers
corresponding cons/alt (two temp2 variables) are checked, cons/alt
themselves are not checked and causing 2 ICEs building
GCC target libraries as of this writing:
1. gcc/libatomic/config/posix/lock.c
2. gcc/libgomp/fortran.c
Coercing a large value into a register will fix the issue.
It also coerce a large cons into a register on "imm, imm" case (the author
could not reproduce but possible to cause an ICE).
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move): Force
large constant cons/alt into a register.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-ice-2.c: New test. This is based on
an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c
but heavily minimized.
---
gcc/config/riscv/riscv.cc | 21 +++++++++++++------
gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 ++++++++++
2 files changed, 26 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d8f7b4f16ed..e306d57814be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3917,6 +3917,11 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
gen_rtx_IF_THEN_ELSE (mode, cond,
CONST0_RTX (mode),
alt)));
+ /* CONS might not fit into a signed 12 bit immediate suitable
+ for an addi instruction. If that's the case, force it
+ into a register. */
+ if (!SMALL_OPERAND (INTVAL (cons)))
+ cons = force_reg (mode, cons);
riscv_emit_binary (PLUS, dest, dest, cons);
return true;
}
@@ -3940,11 +3945,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
rtx temp1 = gen_reg_rtx (mode);
rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode);
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
- for an addi instruction. If that's the case, force it into
- a register. */
+ /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
+ suitable for an addi instruction. If that's the case, force it
+ into a register. */
if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (cons)))
+ cons = force_reg (mode, cons);
riscv_emit_binary (PLUS, temp1, alt, temp2);
emit_insn (gen_rtx_SET (dest,
@@ -3986,11 +3993,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
rtx temp1 = gen_reg_rtx (mode);
rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode);
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
- for an addi instruction. If that's the case, force it into
- a register. */
+ /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
+ suitable for an addi instruction. If that's the case, force it
+ into a register. */
if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (alt)))
+ alt = force_reg (mode, alt);
riscv_emit_binary (PLUS, temp1, cons, temp2);
emit_insn (gen_rtx_SET (dest,
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
new file mode 100644
index 000000000000..ffd8dcb5814e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
+
+#define SOME_NUMBER 0x1000
+
+unsigned long
+d (unsigned long n)
+{
+ return n > SOME_NUMBER ? SOME_NUMBER : n;
+}
base-commit: 72b639760a891c406725854bfb08132c83f0761a
--
2.42.0
next prev parent reply other threads:[~2023-09-05 12:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-04 0:20 [PATCH] " Tsukasa OI
2023-09-04 6:45 ` Kito Cheng
2023-09-05 5:27 ` Jeff Law
2023-09-05 5:30 ` Tsukasa OI
2023-09-05 12:08 ` Tsukasa OI [this message]
2023-09-06 1:22 ` [PATCH v2] " Jeff Law
2023-09-06 1:59 ` Tsukasa OI
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=37a03341f16da30b83bec1f4ef51dce4e6f25264.1693915537.git.research_trasio@irq.a4lg.com \
--to=research_trasio@irq.a4lg.com \
--cc=andrew@sifive.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=jim.wilson.gcc@gmail.com \
--cc=kito.cheng@gmail.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).