From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id DCEFD3836E63 for ; Mon, 6 Jun 2022 22:07:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DCEFD3836E63 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 256KTvPn028142; Mon, 6 Jun 2022 22:07:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3gghbfsfva-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:07:56 +0000 Received: from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 256M7u14007465; Mon, 6 Jun 2022 22:07:56 GMT Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com [169.55.85.253]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3gghbfsfv0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:07:56 +0000 Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1]) by ppma01wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 256LomJX014031; Mon, 6 Jun 2022 22:07:55 GMT Received: from b01cxnp23034.gho.pok.ibm.com (b01cxnp23034.gho.pok.ibm.com [9.57.198.29]) by ppma01wdc.us.ibm.com with ESMTP id 3gfy19g905-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:07:55 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 256M7sEv26214770 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 22:07:54 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 85965124053; Mon, 6 Jun 2022 22:07:54 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 16345124052; Mon, 6 Jun 2022 22:07:54 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:07:53 +0000 (GMT) Message-ID: <3808197933afead6b0b065cfbb3a44df8045965c.camel@vnet.ibm.com> Subject: [PATCH,RS6000 4/5] Replace MASK_ with OPTION_MASK_ From: will schmidt To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool , David Edelsohn , "Kewen.Lin" Date: Mon, 06 Jun 2022 17:07:53 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mqGNXgFD0u5vSWZ-QQKtBpNyNXAE5KEo X-Proofpoint-ORIG-GUID: dzBzR2X1VJTaw68g15swqMkebXEcJXMg Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2022 22:08:00 -0000 [PATCH,RS6000 4/5] Replace MASK_ with OPTION_MASK_ This replaces the MASK_ references with OPTION_MASK_ and removes the now unused defines. This patch removes the defines for MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE. gcc/ * config/rs6000/aix71.h (TARGET_DEFAULT): Replace MASK_MFCRF with OPTION_MASK_MFCRF. * config/rs6000/darwin.h (TARGET_DEFAULT): Replace MASK_MULTIPLE with OPTION_MASK_MULTIPLE. * config/rs6000/darwin64-biarch.h (TARGET_DEFAULT): Same. * config/rs6000/default.h (TARGET_DEFAULT): Replace MASK_MFCRF with OPTION_MASK_MFCRF. * config/rs6000/eabi.h (TARGET_DEFAULT): Replace MASK_EABI with OPTION_MASK_EABI. * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Same. * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Replace MASK_ALTIVEC with OPTION_MASK_ALTIVEC. * config/rs6000/rs6000-cpus.def (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_ISEL, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE): Replace with OPTION_MASK_ALTIVEC, OPTION_MASK_CMPB, OPTION_MASK_CRYPTO, OPTION_MASK_DFP, OPTION_MASK_DIRECT_MOVE, OPTION_MASK_DLMZB, OPTION_MASK_EABI, OPTION_MASK_FLOAT128_KEYWORD, OPTION_MASK_FLOAT128_HW, OPTION_MASK_FPRND, OPTION_MASK_P8_FUSION, OPTION_MASK_HARD_FLOAT, OPTION_MASK_HTM, OPTION_MASK_ISEL, OPTION_MASK_MFCRF, OPTION_MASK_MMA, OPTION_MASK_MULHW, OPTION_MASK_MULTIPLE, OPTION_MASK_NO_UPDATE. * config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace MASK_MFCRF, MASK_ALTIVEC with OPTION_MASK_MFCRF, OPTION_MASK_ALTIVEC. * config/rs6000/rs6000.h (TARGET_DEFAULT): Replace MASK_MULTIPLE with OPTION_MASK_MULTIPLE. (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_ISEL, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE): Delete. * config/rs6000/vxworks.h (TARGET_DEFAULT): Replace MASK_EABI with OPTION_MASK_EABI. diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 57e07bcc65ee..3f7e6e380ca8 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -135,13 +135,14 @@ do { \ #include "rs6000-cpus.def" #undef RS6000_CPU #undef TARGET_DEFAULT #ifdef RS6000_BI_ARCH -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #else -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF) +#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) #endif #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index b5cef42610f7..ec02022c6a9f 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -365,11 +365,11 @@ /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD #define TARGET_IEEEQUAD 0 diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index 57b0fab084e3..a53e567f8b73 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) + | OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" /* Actually, there's really only 970 as an active option. */ diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 4bf0feef2f8e..f3a81404eff3 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -22,14 +22,16 @@ along with GCC; see the file COPYING3. If not see #include "rs6000-cpus.def" #undef RS6000_CPU #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT \ + | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" #endif diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index e58283fe5d4e..367de7bc2700 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" #define INVOKE__main diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index 63cb00fa8054..23cef799a045 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!no-maltivec:-maltivec}}}" #undef SUBSUBTARGET_OVERRIDE_OPTIONS diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index d2557ca57adb..55bae1188369 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -20,14 +20,14 @@ . */ /* Override rs6000.h and sysv4.h definition. */ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_ALTIVEC | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (OPTION_MASK_ALTIVEC | MASK_LITTLE_ENDIAN) #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #endif #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!mno-altivec:-maltivec}}}" diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 963947f69392..7d226493dc54 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -176,24 +176,29 @@ where the arguments are the fields of struct rs6000_ptt. */ RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, - MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB - | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | MASK_PPC_GFXOPT + | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) RS6000_CPU ("476fp", PROCESSOR_PPC476, - MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_MULHW | MASK_DLMZB) + MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND + | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) -RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) +RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE) RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) @@ -204,48 +209,51 @@ RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) +RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) +RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) RS6000_CPU ("a2", PROCESSOR_PPCA2, - MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB - | MASK_NO_UPDATE) + MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | OPTION_MASK_CMPB + | OPTION_MASK_NO_UPDATE) RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 - | MASK_MFCRF | MASK_ISEL) + | OPTION_MASK_MFCRF | OPTION_MASK_ISEL) RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("G5", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB) RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND) RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | MASK_RECIP_PRECISION) RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 6b7a6db9a445..2faac05b5045 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -20727,15 +20727,15 @@ rs6000_darwin_file_start (void) const char *arg; const char *name; HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, + { "970", "ppc970", MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, - { "7400", "ppc7400", MASK_ALTIVEC }, + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, { "750", "ppc750", 0 }, { "740", "ppc750", 0 }, { "G3", "ppc750", 0 }, { "604e", "ppc604e", 0 }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 72eb473acbc3..4d180bd95e59 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -277,11 +277,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #endif #else /* The option machinery will define this. */ #endif -#define TARGET_DEFAULT (MASK_MULTIPLE) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE) /* Define generic processor types based upon current deployment. */ #define PROCESSOR_COMMON PROCESSOR_PPC601 #define PROCESSOR_POWERPC PROCESSOR_PPC604 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A @@ -506,29 +506,10 @@ extern int rs6000_vector_align[]; /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ equivalents are defined here. */ -#define MASK_ALTIVEC OPTION_MASK_ALTIVEC -#define MASK_CMPB OPTION_MASK_CMPB -#define MASK_CRYPTO OPTION_MASK_CRYPTO -#define MASK_DFP OPTION_MASK_DFP -#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE -#define MASK_DLMZB OPTION_MASK_DLMZB -#define MASK_EABI OPTION_MASK_EABI -#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD -#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW -#define MASK_FPRND OPTION_MASK_FPRND -#define MASK_P8_FUSION OPTION_MASK_P8_FUSION -#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT -#define MASK_HTM OPTION_MASK_HTM -#define MASK_ISEL OPTION_MASK_ISEL -#define MASK_MFCRF OPTION_MASK_MFCRF -#define MASK_MMA OPTION_MASK_MMA -#define MASK_MULHW OPTION_MASK_MULHW -#define MASK_MULTIPLE OPTION_MASK_MULTIPLE -#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR #define MASK_P9_MISC OPTION_MASK_P9_MISC #define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 4f6d116929b6..6f11de6c5792 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -225,11 +225,11 @@ along with GCC; see the file COPYING3. If not see #undef LINK_SPEC #define LINK_SPEC VXWORKS_LINK_SPEC " " VXWORKS_RELAX_LINK_SPEC #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (OPTION_MASK_EABI | MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 /* Only big endian PPC is supported by VxWorks. */