From: chenglulu <chenglulu@loongson.cn>
To: Chenghui Pan <panchenghui@loongson.cn>, gcc-patches@gcc.gnu.org
Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn
Subject: Re: [pushed ][PATCH v1] LoongArch: Fix insn output of vec_concat templates for LASX.
Date: Wed, 27 Dec 2023 14:57:11 +0800 [thread overview]
Message-ID: <38626c2e-a417-36fe-6639-2a79914e4db7@loongson.cn> (raw)
In-Reply-To: <20231222082203.888077-1-panchenghui@loongson.cn>
Pused to r14-6848.
在 2023/12/22 下午4:22, Chenghui Pan 写道:
> When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following
> instruction block are being generated by vec_concatv32qi (which is
> generated by vec_initv32qiv16qi) at entrance of foo() function:
>
> vldx $vr3,$r5,$r6
> vld $vr2,$r5,0
> xvpermi.q $xr2,$xr3,0x20
>
> causes the reversion of vec_initv32qiv16qi operation's high and
> low 128-bit part.
>
> According to other target's similar impl and LSX impl for following
> RTL representation, current definition in lasx.md of "vec_concat<mode>"
> are wrong:
>
> (set (op0) (vec_concat (op1) (op2)))
>
> For correct behavior, the last argument of xvpermi.q should be 0x02
> instead of 0x20. This patch fixes this issue and cleanup the vec_concat
> template impl.
>
> gcc/ChangeLog:
>
> * config/loongarch/lasx.md (vec_concatv4di): Delete.
> (vec_concatv8si): Delete.
> (vec_concatv16hi): Delete.
> (vec_concatv32qi): Delete.
> (vec_concatv4df): Delete.
> (vec_concatv8sf): Delete.
> (vec_concat<mode>): New template with insn output fixed.
> ---
> gcc/config/loongarch/lasx.md | 74 ++++--------------------------------
> 1 file changed, 7 insertions(+), 67 deletions(-)
>
> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
> index eeac8cd984b..a9d948bb606 100644
> --- a/gcc/config/loongarch/lasx.md
> +++ b/gcc/config/loongarch/lasx.md
> @@ -590,77 +590,17 @@ (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
> [(set_attr "type" "simd_insert")
> (set_attr "mode" "<MODE>")])
>
> -(define_insn "vec_concatv4di"
> - [(set (match_operand:V4DI 0 "register_operand" "=f")
> - (vec_concat:V4DI
> - (match_operand:V2DI 1 "register_operand" "0")
> - (match_operand:V2DI 2 "register_operand" "f")))]
> - "ISA_HAS_LASX"
> -{
> - return "xvpermi.q\t%u0,%u2,0x20";
> -}
> - [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DI")])
> -
> -(define_insn "vec_concatv8si"
> - [(set (match_operand:V8SI 0 "register_operand" "=f")
> - (vec_concat:V8SI
> - (match_operand:V4SI 1 "register_operand" "0")
> - (match_operand:V4SI 2 "register_operand" "f")))]
> - "ISA_HAS_LASX"
> -{
> - return "xvpermi.q\t%u0,%u2,0x20";
> -}
> - [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DI")])
> -
> -(define_insn "vec_concatv16hi"
> - [(set (match_operand:V16HI 0 "register_operand" "=f")
> - (vec_concat:V16HI
> - (match_operand:V8HI 1 "register_operand" "0")
> - (match_operand:V8HI 2 "register_operand" "f")))]
> - "ISA_HAS_LASX"
> -{
> - return "xvpermi.q\t%u0,%u2,0x20";
> -}
> - [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DI")])
> -
> -(define_insn "vec_concatv32qi"
> - [(set (match_operand:V32QI 0 "register_operand" "=f")
> - (vec_concat:V32QI
> - (match_operand:V16QI 1 "register_operand" "0")
> - (match_operand:V16QI 2 "register_operand" "f")))]
> - "ISA_HAS_LASX"
> -{
> - return "xvpermi.q\t%u0,%u2,0x20";
> -}
> - [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DI")])
> -
> -(define_insn "vec_concatv4df"
> - [(set (match_operand:V4DF 0 "register_operand" "=f")
> - (vec_concat:V4DF
> - (match_operand:V2DF 1 "register_operand" "0")
> - (match_operand:V2DF 2 "register_operand" "f")))]
> - "ISA_HAS_LASX"
> -{
> - return "xvpermi.q\t%u0,%u2,0x20";
> -}
> - [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DF")])
> -
> -(define_insn "vec_concatv8sf"
> - [(set (match_operand:V8SF 0 "register_operand" "=f")
> - (vec_concat:V8SF
> - (match_operand:V4SF 1 "register_operand" "0")
> - (match_operand:V4SF 2 "register_operand" "f")))]
> +(define_insn "vec_concat<mode>"
> + [(set (match_operand:LASX 0 "register_operand" "=f")
> + (vec_concat:LASX
> + (match_operand:<VHMODE256_ALL> 1 "register_operand" "0")
> + (match_operand:<VHMODE256_ALL> 2 "register_operand" "f")))]
> "ISA_HAS_LASX"
> {
> - return "xvpermi.q\t%u0,%u2,0x20";
> + return "xvpermi.q\t%u0,%u2,0x02";
> }
> [(set_attr "type" "simd_splat")
> - (set_attr "mode" "V4DI")])
> + (set_attr "mode" "<MODE>")])
>
> ;; xshuf.w
> (define_insn "lasx_xvperm_<lasxfmt_f_wd>"
prev parent reply other threads:[~2023-12-27 6:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-22 8:22 [PATCH " Chenghui Pan
2023-12-27 6:57 ` chenglulu [this message]
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