From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 81418 invoked by alias); 9 Jun 2017 12:54:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80953 invoked by uid 89); 9 Jun 2017 12:54:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=abilities, era, Hx-languages-length:4434, chk X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:17 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQg-0007YH-AH for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:20 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQf-0007Te-W3 for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC1932B; Fri, 9 Jun 2017 05:54:17 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 36D893F3E1; Fri, 9 Jun 2017 05:54:17 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 12/30] [arm] Allow new extended syntax CPU and architecture names during configure Date: Fri, 09 Jun 2017 12:54:00 -0000 Message-Id: <3868848ea778bb498c716d5d8bad2c5b4c1cc2e4.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.7.4" X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 X-SW-Source: 2017-06/txt/msg00617.txt.bz2 This is a multi-part message in MIME format. --------------2.7.4 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 831 This patch extends support for the new extended-style architecture strings to configure and the target default options. We validate any options passed by the user to configure against the permitted extensions for that CPU or architecture. * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real cpu name. (arm*-*-*): Set target_cpu_default2 to a quoted string. * config/arm/parsecpu.awk (check_cpu): Validate any extension options. (check_arch): Likewise. * config/arm/arm.c (arm_configure_build_target): Handle TARGET_CPU_DEFAULT being a string constant. Scan any feature options in the default. --- gcc/config.gcc | 6 +++--- gcc/config/arm/arm.c | 8 +++++++- gcc/config/arm/parsecpu.awk | 36 ++++++++++++++++++++++++++++-------- 3 files changed, 38 insertions(+), 12 deletions(-) --------------2.7.4 Content-Type: text/x-patch; name="0012-arm-Allow-new-extended-syntax-CPU-and-architecture-n.patch" Content-Disposition: attachment; filename="0012-arm-Allow-new-extended-syntax-CPU-and-architecture-n.patch" Content-Transfer-Encoding: quoted-printable Content-length: 3899 diff --git a/gcc/config.gcc b/gcc/config.gcc index f55dcaa..4d0f7ec 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1159,7 +1159,7 @@ arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems* | a= rm*-*-fuchsia*) arm*-*-fuchsia*) tm_file=3D"${tm_file} fuchsia.h arm/fuchsia-elf.h glibc-stdint.h" tmake_file=3D"${tmake_file} arm/t-bpabi" - target_cpu_cname=3D"genericv7a" + target_cpu_cname=3D"generic-armv7-a" ;; arm*-*-rtems*) tm_file=3D"${tm_file} rtems.h arm/rtems.h newlib-stdint.h" @@ -4494,9 +4494,9 @@ case ${target} in arm*-*-*) if test x$target_cpu_cname =3D x then - target_cpu_default2=3DTARGET_CPU_arm6 + target_cpu_default2=3D"\\\"arm6\\\"" else - target_cpu_default2=3DTARGET_CPU_$target_cpu_cname + target_cpu_default2=3D"\\\"$target_cpu_cname\\\"" fi ;; =20 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 73b1369..7296ad3 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3161,7 +3161,9 @@ arm_configure_build_target (struct arm_build_target *= target, bitmap_clear (sought_isa); auto_sbitmap default_isa (isa_num_bits); =20 - arm_selected_cpu =3D &all_cores[TARGET_CPU_DEFAULT]; + arm_selected_cpu =3D arm_parse_cpu_option_name (all_cores, "default = CPU", + TARGET_CPU_DEFAULT); + cpu_opts =3D strchr (TARGET_CPU_DEFAULT, '+'); gcc_assert (arm_selected_cpu->common.name); =20 /* RWE: All of the selection logic below (to the end of this @@ -3172,6 +3174,8 @@ arm_configure_build_target (struct arm_build_target *= target, support for the pre-thumb era cores is removed. */ sel =3D arm_selected_cpu; arm_initialize_isa (default_isa, sel->common.isa_bits); + arm_parse_option_features (default_isa, &arm_selected_cpu->common, + cpu_opts); =20 /* Now check to see if the user has specified any command line switches that require certain abilities from the cpu. */ @@ -3259,6 +3263,8 @@ arm_configure_build_target (struct arm_build_target *= target, structure. */ target->core_name =3D arm_selected_cpu->common.name; arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits); + arm_parse_option_features (target->isa, &arm_selected_cpu->common, + cpu_opts); arm_selected_arch =3D all_architectures + arm_selected_cpu->arch; } =20 diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 61e8bc2..b6e5093 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -393,9 +393,19 @@ function gen_opt () { } =20 function check_cpu (name) { - if (name in cpu_cnames) { - print cpu_cnames[name] - } else print "error" + exts =3D split (name, extensions, "+") + + if (! extensions[1] in cpu_cnames) { + return "error" + } + + for (n =3D 2; n <=3D exts; n++) { + if (!((extensions[1], extensions[n]) in cpu_opt_remove) \ + && !((extensions[1], extensions[n]) in cpu_optaliases)) { + return "error" + } + } + return name } =20 function check_fpu (name) { @@ -405,9 +415,19 @@ function check_fpu (name) { } =20 function check_arch (name) { - if (name in arch_isa) { - print name - } else print "error" + exts =3D split (name, extensions, "+") + + if (! extensions[1] in arch_isa) { + return "error" + } + + for (n =3D 2; n <=3D exts; n++) { + if (!((extensions[1], extensions[n]) in arch_opt_remove) \ + && !((extensions[1], extensions[n]) in arch_optaliases)) { + return "error" + } + } + return name } =20 BEGIN { @@ -614,10 +634,10 @@ END { gen_opt() } else if (cmd ~ /^chk(cpu|tune) /) { split (cmd, target) - check_cpu(target[2]) + print check_cpu(target[2]) } else if (cmd ~ /^chkarch /) { split (cmd, target) - check_arch(target[2]) + print check_arch(target[2]) } else if (cmd ~ /^chkfpu /) { split (cmd, target) check_fpu(target[2]) --------------2.7.4--