The following patch changes the method of scheduling vector and vector
load insns. Before it tried to pair up like insns and interleave the
pairs, resulting in something like L1L2V1V2. The preferred scheduling is
now to just interleave the insns, resulting in L1V1L2V2. If interleaving
fails, fall back to pairing like insns.

Bootstrap/regtest on powerpc64le-linux with no new regressions. I also
did a -mcpu=power9 build of CPU2006 with no errors. Ok for trunk and
backport to GCC 6 branch?

-Pat



2017-04-07  Pat Haugen  <pthaugen@us.ibm.com>

	* rs6000/rs6000.c (vec_load_pendulum): Rename...
	(vec_pairing): ...to this.
	(power9_sched_reorder2): Rewrite code for pairing vector/vecload insns.
	(rs6000_sched_init): Adjust for name change.
	(struct rs6000_sched_context): Likewise.
	(rs6000_init_sched_context): Likewise.
	(rs6000_set_sched_context): Likewise.