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Wed, 31 Jul 2024 20:49:51 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0C67E58054; Wed, 31 Jul 2024 20:49:49 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 033C55805A; Wed, 31 Jul 2024 20:49:48 +0000 (GMT) Received: from [9.67.189.147] (unknown [9.67.189.147]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTP; Wed, 31 Jul 2024 20:49:47 +0000 (GMT) Message-ID: <391ddc80-a9d3-45d7-a6a5-ddd79e9ebb97@linux.ibm.com> Date: Wed, 31 Jul 2024 13:49:47 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH ver 2] rs6000, Add new overloaded vector shift builtin int128, varients To: "Kewen.Lin" , cel Cc: GCC Patches , Peter Bergner , segher , David Edelsohn References: Content-Language: en-US From: Carl Love In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mVQeUCXOwzd95ar-M-SoVqTJAka0wdL8 X-Proofpoint-ORIG-GUID: 0-0A0wBQ1BPEEoAh5ILxIVJfzm-I6Ssx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-31_10,2024-07-31_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 spamscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407310140 X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Kewen: On 7/29/24 3:21 AM, Kewen.Lin wrote: >> +@smallexample >> +@exdent vector signed __int128 vec_sld (vector signed __int128, >> +vector signed __int128, const unsigned int); >> +@exdent vector unsigned __int128 vec_sld (vector unsigned __int128, >> +vector unsigned __int128, const unsigned int); >> +@exdent vector signed __int128 vec_sldw (vector signed __int128, >> +vector signed __int128, const unsigned int); >> +@exdent vector unsigned __int128 vec_sldw (vector unsigned __int, >> +vector unsigned __int128, const unsigned int); >> +@exdent vector signed __int128 vec_slo (vector signed __int128, >> +vector signed char); >> +@exdent vector signed __int128 vec_slo (vector signed __int128, >> +vector unsigned char); >> +@exdent vector unsigned __int128 vec_slo (vector unsigned __int128, >> +vector signed char); >> +@exdent vector unsigned __int128 vec_slo (vector unsigned __int128, >> +vector unsigned char); >> +@exdent vector signed __int128 vec_sro (vector signed __int128, >> +vector signed char); >> +@exdent vector signed __int128 vec_sro (vector signed __int128, >> +vector unsigned char); >> +@exdent vector unsigned __int128 vec_sro (vector unsigned __int128, >> +vector signed char); >> +@exdent vector unsigned __int128 vec_sro (vector unsigned __int128, >> +vector unsigned char); >> +@exdent vector signed __int128 vec_srl (vector signed __int128, >> +vector unsigned char); >> +@exdent vector unsigned __int128 vec_srl (vector unsigned __int128, >> +vector unsigned char); >> +@end smallexample >> + >> +The above instances are extension of the existing overloaded built-ins >> +@code{vec_sld}, @code{vec_sldw}, @code{vec_slo}, @code{vec_sro}, @code{vec_srl} >> +that are documented in the PVIPR. >> + >>  @findex vec_srdb > Nit: The above new @smallexample section and its associated description should be > placed after this @findex vec_srdb (otherwise it breaks the connection between the > index and the content of vec_srdb), Yes, my bad.  I didn't notice I got the findex vec_srdb in the wrong place. > but personally I preferred it to be placed at > the end of this node, that is: after > "int vec_any_le (vector unsigned __int128, vector unsigned __int128); > @end smallexample > " as what's in your previous version, since most of these beginning entries have > their headings but this @smallexample section doesn't have a heading, it looks a > bit weird. OK, perhaps I didn't understand where you wanted it in the previous email.  I moved it.  Hopefully I have it correct this time. >>  Vector Splat >> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shift-double-runnable-int128.c b/gcc/testsuite/gcc.target/powerpc/vec-shift-double-runnable-int128.c >> new file mode 100644 >> index 00000000000..65e8e94ec07 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/powerpc/vec-shift-double-runnable-int128.c >> @@ -0,0 +1,358 @@ >> +/* { dg-do run  { target power10_hw } } */ >> +/* { dg-do link { target { ! power10_hw } } } */ >> +/* { dg-require-effective-target power10_ok } */ > As Peter pointed out in another thread, you need int128 effective target check as well, > otherwise it will fail with power10 -m32. > > Another nit: power10_hw should already guarantee power10_ok, so power10_ok > is only required for dg-do link. Changed to: +/* { dg-do run  { target power10_hw } } */ +/* { dg-do compile  { target { ! power10_hw } } } */ +/* { dg-require-effective-target int128 } */ per the discussion/feedback from Kewen and Peter.                                      Carl