[PATCH 0/4] GCC port for the Visium

[PATCH 0/4] GCC port for the Visium

[Eric Botcazou]

Hi,

on behalf of Controls and Data Services, AdaCore would like to contribute a
port of the GCC to the Visium.  This is a 32-bit RISC architecture with an 
Extended Arithmetic Module implementing some 64-bit operations and an FPU
designed for embedded systems.  The binutils port has already been contributed 
and the ultimate goal is to contribute a port of the entire toolchain with 
simulator, debugger and embedded libc.

The original port had been written by employees of CDS or companies that
are now part of CDS, and AdaCore contributed enhancements and modifications
on top of it.  Both companies have a copyright assignment on file with the
FSF for the various components of the toolchain.

The Visium is a classic 32-bit RISC architecture whose branches have a delay 
slot and whose arithmetic and logical instructions all set the flags, and 
they comprise the moves between GP registers (which are inclusive ORs under 
the hood in the traditional RISC fashion).  The port is nevertheless MODE_CC 
and it generates code that is as good as the original cc0 implementation with 
the help of the post-reload compare elimination pass (modulo a small patch for 
the reorg pass that I'll submit separately).

The GCC port is split into 4 patches (toplevel, libgcc, gcc, gcc/testsuite) 
and is C-only for now, and 'make -k check-c' reports the following results:

Target is visium-unknown-elf
Host   is x86_64-suse-linux-gnu

		=== gcc tests ===


Running target visium-sim
FAIL: gcc.dg/torture/builtin-explog-1.c   -O1  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O2  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O2 -flto -fno-use-linker-plugin -
flto-partition=none  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O3 -fomit-frame-pointer  (test for 
excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O3 -g  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -Os  (test for excess errors)

		=== gcc Summary for visium-sim ===

# of expected passes		81007
# of unexpected failures	6
# of expected failures		94
# of unsupported tests		1796

Running target visium-sim/-mcpu=gr6
FAIL: gcc.dg/torture/builtin-explog-1.c   -O1  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O2  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O2 -flto -fno-use-linker-plugin -
flto-partition=none  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O3 -fomit-frame-pointer  (test for 
excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -O3 -g  (test for excess errors)
FAIL: gcc.dg/torture/builtin-explog-1.c   -Os  (test for excess errors)

		=== gcc Summary for visium-sim/-mcpu=gr6 ===

# of expected passes		81007
# of unexpected failures	6
# of expected failures		94
# of unsupported tests		1796

		=== gcc Summary ===

# of expected passes		162014
# of unexpected failures	12
# of expected failures		188
# of unsupported tests		3592
/home/eric/build/gcc/visium-elf/gcc/xgcc  version 5.0.0 20141211 
(experimental) [trunk revision 218617] (GCC) 

after they are applied (on a x86_64-linux host).  I think that the failures 
are common to all newlib targets and very likely related to:
  https://gcc.gnu.org/ml/gcc-patches/2014-12/msg00357.html

OK for the mainline?

-- 
Eric Botcazou

[PATCH 1/4] Add Visium support to toplevel

[Eric Botcazou]

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ChangeLog

2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>

	* config.sub: Update from upstream config repo.
	* configure.ac: Add Visium support.
	* configure: Regenerate.


-- 
Eric Botcazou

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Index: config.sub
===================================================================
--- config.sub	(revision 218617)
+++ config.sub	(working copy)
@@ -2,7 +2,7 @@
 # Configuration validation subroutine script.
 #   Copyright 1992-2014 Free Software Foundation, Inc.
 
-timestamp='2014-09-26'
+timestamp='2014-12-03'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
@@ -313,6 +313,7 @@ case $basic_machine in
 	| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
 	| ubicom32 \
 	| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
+	| visium \
 	| we32k \
 	| x86 | xc16x | xstormy16 | xtensa \
 	| z8k | z80)
@@ -440,6 +441,7 @@ case $basic_machine in
 	| ubicom32-* \
 	| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
 	| vax-* \
+	| visium-* \
 	| we32k-* \
 	| x86-* | x86_64-* | xc16x-* | xps100-* \
 	| xstormy16-* | xtensa*-* \
Index: configure.ac
===================================================================
--- configure.ac	(revision 218617)
+++ configure.ac	(working copy)
@@ -669,6 +669,10 @@ case "${target}" in
     # for explicit misaligned loads.
     noconfigdirs="$noconfigdirs target-libssp"
     ;;
+  visium-*-*)
+    # No hosted I/O support.
+    noconfigdirs="$noconfigdirs target-libssp"
+    ;;
 esac
 
 # Disable libstdc++-v3 for some systems.

[PATCH 2/4] Add Visium support to libgcc

[Eric Botcazou]

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libgcc/ChangeLog

2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>
        
	* config.host: Add Visium support.
	* config/visium: New directory.


-- 
Eric Botcazou

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Index: config.host
===================================================================
--- config.host	(revision 218617)
+++ config.host	(working copy)
@@ -1233,6 +1233,10 @@ vax-*-netbsdelf*)
 	;;
 vax-*-openbsd*)
 	;;
+visium-*-elf*)
+        extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+        tmake_file="visium/t-visium t-fdpbit"
+        ;;
 xstormy16-*-elf)
 	tmake_file="stormy16/t-stormy16 t-fdpbit"
 	;;

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[PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

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gcc/ChangeLog

2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>

	* config.gcc: Add Visium support.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* doc/invoke.texi: Document Visium options.
	* doc/md.texi: Document Visium constraints.
	* common/config/visium: New directory.
	* config/visium: Likewise.


-- 
Eric Botcazou

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Index: config.gcc
===================================================================
--- config.gcc	(revision 218617)
+++ config.gcc	(working copy)
@@ -2853,6 +2853,10 @@ vax-*-openbsd*)
 	extra_options="${extra_options} openbsd.opt"
 	use_collect2=yes
 	;;
+visium-*-elf*)
+	tm_file="dbxelf.h elfos.h ${tm_file} visium/elf.h newlib-stdint.h"
+	tmake_file="visium/t-visium visium/t-crtstuff"
+	;;
 xstormy16-*-elf)
 	# For historical reasons, the target files omit the 'x'.
 	tm_file="dbxelf.h elfos.h newlib-stdint.h stormy16/stormy16.h"
Index: configure.ac
===================================================================
--- configure.ac	(revision 218617)
+++ configure.ac	(working copy)
@@ -4442,7 +4442,7 @@ esac
 case "$cpu_type" in
   aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
   | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
-  | xstormy16 | xtensa)
+  | visium | xstormy16 | xtensa)
     insn="nop"
     ;;
   ia64 | s390)
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi	(revision 218617)
+++ doc/invoke.texi	(working copy)
@@ -1062,6 +1062,10 @@ See RS/6000 and PowerPC Options.
 @emph{VAX Options}
 @gccoptlist{-mg  -mgnu  -munix}
 
+@emph{Visium Options}
+@gccoptlist{-mdebug -msim -mfpu -mno-fpu -mhard-float -msoft-float @gol
+-mcpu=@var{cpu-type} -mtune=@var{cpu-type} -msv-mode -muser-mode}
+
 @emph{VMS Options}
 @gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64 @gol
 -mpointer-size=@var{size}}
@@ -11845,6 +11849,7 @@ platform.
 * TILEPro Options::
 * V850 Options::
 * VAX Options::
+* Visium Options::
 * VMS Options::
 * VxWorks Options::
 * x86-64 Options::
@@ -22456,6 +22461,77 @@ GNU assembler is being used.
 Output code for G-format floating-point numbers instead of D-format.
 @end table
 
+@node Visium Options
+@subsection Visium Options
+@cindex Visium options
+
+@table @gcctabopt
+
+@item -mdebug
+@opindex mdebug
+A program which performs file I/O and is destined to run on an MCM target
+should be linked with this option.  It causes the libraries libc.a and
+libdebug.a to be linked.  The program should be run on the target under
+the control of the GDB remote debugging stub.
+
+@item -msim
+@opindex msim
+A program which performs file I/O and is destined to run on the simulator
+should be linked with option.  This causes libraries libc.a and libsim.a to
+be linked.
+
+@item -mfpu
+@itemx -mhard-float
+@opindex mfpu
+@opindex mhard-float
+Generate code containing floating-point instructions.  This is the
+default.
+
+@item -mno-fpu
+@itemx -msoft-float
+@opindex mno-fpu
+@opindex msoft-float
+Generate code containing library calls for floating-point.
+
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option.  In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
+
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type @var{cpu_type}.  Supported values for @var{cpu_type} are
+@samp{mcm}, @samp{gr5} and @samp{gr6}.
+
+@samp{mcm} is a synonym of @samp{gr5} present for backward compatibility.
+
+By default (unless configured otherwise), GCC generates code for the GR5
+variant of the Visium architecture.  
+
+With @option{-mcpu=gr6}, GCC generates code for the GR6 variant of the Visium
+architecture.  The only difference from GR5 code is that the compiler will
+generate block move instructions.
+
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type @var{cpu_type},
+but do not set the instruction set or register set that the option
+@option{-mcpu=@var{cpu_type}} would.
+
+@item -msv-mode
+@opindex msv-mode
+Generate code for the supervisor mode, where there are no restrictions on
+the access to general registers.  This is the default.
+
+@item -muser-mode
+@opindex muser-mode
+Generate code for the user mode, where the access to some general registers
+is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
+mode; on the GR6, only registers r29 to r31 are affected.
+@end table
+
 @node VMS Options
 @subsection VMS Options
 
Index: doc/md.texi
===================================================================
--- doc/md.texi	(revision 218642)
+++ doc/md.texi	(working copy)
@@ -3974,6 +3974,56 @@ A 2-element vector constant with identic
 
 @end table
 
+@item Visium---@file{config/visium/constraints.md}
+@table @code
+@item b
+EAM register @code{mdb}
+
+@item c
+EAM register @code{mdc}
+
+@item f
+Floating point register
+
+@ifset INTERNALS
+@item k
+Register for sibcall optimization
+@end ifset
+
+@item l
+General register, but not @code{r29}, @code{r30} and @code{r31}
+
+@item t
+Register @code{r1}
+
+@item u
+Register @code{r2}
+
+@item v
+Register @code{r3}
+
+@item G
+Floating-point constant 0.0
+
+@item J
+Integer constant in the range 0 .. 65535 (16-bit immediate)
+
+@item K
+Integer constant in the range 1 .. 31 (5-bit immediate)
+
+@item L
+Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
+
+@item M
+Integer constant @minus{}1
+
+@item O
+Integer constant 0
+
+@item P
+Integer constant 32
+@end table
+
 @item Xtensa---@file{config/xtensa/constraints.md}
 @table @code
 @item a
Index: common/config/visium/visium-common.c
===================================================================
--- common/config/visium/visium-common.c	(revision 0)
+++ common/config/visium/visium-common.c	(revision 0)
@@ -0,0 +1,38 @@
+/* Common hooks for Visium.
+   Copyright (C) 2002-2014 Free Software Foundation, Inc.
+   Contributed by C.Nettleton,J.P.Parkes and P.Garbett.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+
+/* Set default optimization options.  */
+static const struct default_options visium_option_optimization_table[] =
+  {
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
+  };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE visium_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

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[PATCH 4/4] Add Visium support to gcc/testsuite

[Eric Botcazou]

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gcc/testsuite/ChangeLog:

2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>

	* lib/target-supports.exp (check_profiling_available): Return 0 for
	Visium.
	(check_effective_target_tls_runtime): Likewise.
	(check_effective_target_logical_op_short_circuit): Return 1 for Visium.
	* gcc.dg/20020312-2.c: Adjust for Visium.
	* gcc.dg/tls/thr-cse-1.c: Likewise
	* gcc.dg/tree-ssa/20040204-1.c: Likewise
	* gcc.dg/tree-ssa/loop-1.c: Likewise.
	* gcc.dg/weak/typeof-2.c: Likewise.


-- 
Eric Botcazou

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Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp	(revision 218617)
+++ lib/target-supports.exp	(working copy)
@@ -538,6 +540,7 @@ proc check_profiling_available { test_wh
 	     || [istarget powerpc-*-elf]
 	     || [istarget rx-*-*]	
 	     || [istarget tic6x-*-elf]
+	     || [istarget visium-*-*]
 	     || [istarget xstormy16-*]
 	     || [istarget xtensa*-*-elf]
 	     || [istarget *-*-rtems*]
@@ -707,9 +710,9 @@ proc check_effective_target_tls_emulated
 # Return 1 if TLS executables can run correctly, 0 otherwise.
 
 proc check_effective_target_tls_runtime {} {
-    # MSP430 runtime does not have TLS support, but just
+    # The runtime does not have TLS support, but just
     # running the test below is insufficient to show this.
-    if { [istarget msp430-*-*] } {
+    if { [istarget msp430-*-*] || [istarget visium-*-*] } {
 	return 0
     }
     return [check_runtime tls_runtime {
@@ -6085,6 +6088,7 @@ proc check_effective_target_logical_op_s
 	 || [istarget s390*-*-*]
 	 || [istarget powerpc*-*-*]
 	 || [istarget nios2*-*-*]
+	 || [istarget visium-*-*]
 	 || [check_effective_target_arm_cortex_m] } {
 	return 1
     }
Index: gcc.dg/weak/typeof-2.c
===================================================================
--- gcc.dg/weak/typeof-2.c	(revision 218617)
+++ gcc.dg/weak/typeof-2.c	(working copy)
@@ -48,4 +48,6 @@ int bar3 (int x)
 // { dg-final { if [string match m68k-*-* $target_triplet ] {return} } }
 // Likewise for moxie targets.
 // { dg-final { if [string match moxie-*-* $target_triplet ] {return} } }
+// Likewise for Visium targets.
+// { dg-final { if [string match visium-*-* $target_triplet ] {return} } }
 // { dg-final { scan-assembler "baz3.*baz3.*baz3.*baz3.*baz3.*baz3" } }
Index: gcc.dg/tree-ssa/loop-1.c
===================================================================
--- gcc.dg/tree-ssa/loop-1.c	(revision 218617)
+++ gcc.dg/tree-ssa/loop-1.c	(working copy)
@@ -49,7 +49,7 @@ int xxx(void)
 /* CRIS keeps the address in a register.  */
 /* m68k sometimes puts the address in a register, depending on CPU and PIC.  */
 
-/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* } } } */
+/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* } } } */
 /* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
 /* { dg-final { scan-assembler-times "= foo"  5 { target ia64*-*-* } } } */
 /* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */
@@ -57,3 +57,4 @@ int xxx(void)
 /* { dg-final { scan-assembler-times "jsr|bsrf|blink\ttr?,r18"  5 { target sh*-*-* } } } */
 /* { dg-final { scan-assembler-times "Jsr \\\$r" 5 { target cris-*-* } } } */
 /* { dg-final { scan-assembler-times "\[jb\]sr" 5 { target fido-*-* m68k-*-* } } } */
+/* { dg-final { scan-assembler-times "bra *tr,r\[1-9\]*,r21" 5 { target visium-*-* } } } */
Index: gcc.dg/tree-ssa/20040204-1.c
===================================================================
--- gcc.dg/tree-ssa/20040204-1.c	(revision 218617)
+++ gcc.dg/tree-ssa/20040204-1.c	(working copy)
@@ -33,5 +33,5 @@ void test55 (int x, int y)
    that the && should be emitted (based on BRANCH_COST).  Fix this
    by teaching dom to look through && and register all components
    as true.  */
-/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* sparc*-*-* spu-*-* x86_64-*-*" } } } } */
+/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-*" } } } } */
 /* { dg-final { cleanup-tree-dump "optimized" } } */
Index: gcc.dg/tls/thr-cse-1.c
===================================================================
--- gcc.dg/tls/thr-cse-1.c	(revision 218617)
+++ gcc.dg/tls/thr-cse-1.c	(working copy)
@@ -18,11 +18,11 @@ int foo (int b, int c, int d)
   return a;
 }
 
-/* { dg-final { scan-assembler-not "emutls_get_address.*emutls_get_address.*" { target { ! { "*-wrs-vxworks"  "*-*-darwin8"  "hppa*-*-hpux*" "spu-*-*" "i?86-*-mingw*" "x86_64-*-mingw*" } } } } } */
+/* { dg-final { scan-assembler-not "emutls_get_address.*emutls_get_address.*" { target { ! { "*-wrs-vxworks"  "*-*-darwin8"  "hppa*-*-hpux*" "spu-*-*" "i?86-*-mingw*" "x86_64-*-mingw*" visium-*-* } } } } } */
 /* { dg-final { scan-assembler-not "call\tL___emutls_get_address.stub.*call\tL___emutls_get_address.stub.*" { target "*-*-darwin8" } } } */
 /* { dg-final { scan-assembler-not "(b,l|bl) __emutls_get_address.*(b,l|bl) __emutls_get_address.*" { target "hppa*-*-hpux*" } } } */
 /* { dg-final { scan-assembler-not "(brsl|brasl)\t__emutls_get_address.*(brsl|brasl)\t__emutls_get_address.*" { target spu-*-* } } } */
 /* { dg-final { scan-assembler-not "tls_lookup.*tls_lookup.*" { target *-wrs-vxworks } } } */
 /* { dg-final { scan-assembler-not "call\t___emutls_get_address.*call\t___emutls_get_address" { target "i?86-*-mingw*" } } } */
 /* { dg-final { scan-assembler-not "call\t__emutls_get_address.*call\t__emutls_get_address" { target "x86_64-*-mingw*" } } } */
-
+/* { dg-final { scan-assembler-not "%l __emutls_get_address.*%l __emutls_get_address" { target visium-*-* } } } */
Index: gcc.dg/20020312-2.c
===================================================================
--- gcc.dg/20020312-2.c	(revision 218617)
+++ gcc.dg/20020312-2.c	(working copy)
@@ -80,6 +80,8 @@ extern void abort (void);
 /* No pic register.  */
 #elif defined(__vax__)
 /* No pic register.  */
+#elif defined(__VISIUM__)
+/* No pic register.  */
 #elif defined(__xstormy16__)
 /* No pic register.  */
 #elif defined(__XTENSA__)

Re: [PATCH 2/4] Add Visium support to libgcc

[Joseph Myers]

Do you have a reason for using fp-bit instead of soft-fp?

libgcc files are generally GPL+exception, not LGPL without exception with 
a very old FSF address (config/visium/div64.c, mod64.c, 
set_trampoline_parity.c, udiv64.c, udivmod64.c, umod64.c)

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH 3/4] Add Visium support to gcc

[Joseph Myers]

Use of `%s' in diagnostics is long obsoleted by %qs (in this case, using 
%qE with the identifier directly, rather than using IDENTIFIER_POINTER, is 
preferred).

INTVAL / UINTVAL return HOST_WIDE_INT / unsigned HOST_WIDE_INT, not long / 
unsigned long.  You have lots of uses of fprintf that presume they return 
long / unsigned long.

As you have the interrupt attribute, you need to add this port to the list 
in extend.texi of ports with this attribute.  (Generally, check the 
checklist of pieces in sourcebuild.texi to update for a new port.)

At least one target for this port should be added to 
contrib/config-list.mk (and you should verify that the port builds cleanly 
with --enable-werror-always, for both 32-bit and 64-bit hosts, when 
building using current trunk GCC).

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH 3/4] Add Visium support to gcc

[Hans-Peter Nilsson]

On Fri, 12 Dec 2014, Joseph Myers wrote:
> At least one target for this port should be added to
> contrib/config-list.mk (and you should verify that the port builds cleanly
> with --enable-werror-always, for both 32-bit and 64-bit hosts, when
> building using current trunk GCC).

While doing that, beware that gcc has bugs causing some ports (I
forgot which ones) to get at least one spurious warning
apparently not attributable to the quality of the port.

PR(s) duly entered, but I can't quote the numbers (finding PRs
is not practical for me after the https change, but IIRC Joern
was the author).

brgds, H-P
PS. of course no excuse to not get the low-hanging fruit.

Re: [PATCH 0/4] GCC port for the Visium

[Mike Stump]

On Dec 11, 2014, at 4:05 PM, Eric Botcazou <ebotcazou@adacore.com> wrote:
> on behalf of Controls and Data Services, AdaCore would like to contribute a
> port of the GCC to the Visium.

> OK for the mainline?

The test suite bits are usual and customary.  I’ll Ok them explicitly anyway.  I’m fine with new ports going in with usual and customary test suite things.

Re: [PATCH 2/4] Add Visium support to libgcc

[Eric Botcazou]

> Do you have a reason for using fp-bit instead of soft-fp?

Apart from the obvious historical reason, probably not, but recently added 
ports (Blackfin, Epiphany) also use it so I'm not sure we want to change it.

> libgcc files are generally GPL+exception, not LGPL without exception with
> a very old FSF address (config/visium/div64.c, mod64.c,
> set_trampoline_parity.c, udiv64.c, udivmod64.c, umod64.c)

Files whose copyright/origin is clear are already GPL+exception, but these 6 
files were originally imported from Glibc so they aren't in the same basket.

I guess I can reuse the copyright notice of soft-fp for them.

-- 
Eric Botcazou

Re: [PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

> Use of `%s' in diagnostics is long obsoleted by %qs (in this case, using
> %qE with the identifier directly, rather than using IDENTIFIER_POINTER, is
> preferred).

Only occurrence fixed by mimicing the i386 port.

> INTVAL / UINTVAL return HOST_WIDE_INT / unsigned HOST_WIDE_INT, not long /
> unsigned long.  You have lots of uses of fprintf that presume they return
> long / unsigned long.

Changed into HOST_WIDE_INT_PRINT_DEC/HOST_WIDE_INT_PRINT_UNSIGNED.

> As you have the interrupt attribute, you need to add this port to the list
> in extend.texi of ports with this attribute.  (Generally, check the
> checklist of pieces in sourcebuild.texi to update for a new port.)

Done.  But there is a bit of a contradiction in sourcebuild.texi:

   * Entries in `gcc/doc/install.texi' for all target triplets
     supported with this target architecture, giving details of any
     special notes about installation for this target, or saying that
     there are no special notes if there are none.

But gcc/doc/install.texi has:

Note that this list of install notes is @emph{not} a list of supported
hosts or targets.  Not all supported hosts and targets are listed
here, only the ones that require host-specific or target-specific
information have to. 

I have nevertheless added visium-*-elf to gcc/doc/install.texi.

I'll note that libbacktrace, libcc1, libcilkrts, liboffloadmic, libsanitizer 
and libvtv are not documented in there.

> At least one target for this port should be added to contrib/config-list.mk

This is documented in sourcebuild.texi, I'll take the 5 steps covered by "If 
the back end is added to the official GCC source repository, the following are 
also necessary:" when the premise is fulfilled.

> (and you should verify that the port builds cleanly with --enable-werror
> -always, for both 32-bit and 64-bit hosts, when building using current trunk 
> GCC).

Do you mean a bootstrap of the cross-compiler with --enable-werror-always on a 
32-bit and a 64-bit host?  OK, I'll do that.

Thanks for the review.

-- 
Eric Botcazou

Re: [PATCH 2/4] Add Visium support to libgcc

[Joseph Myers]

On Mon, 15 Dec 2014, Eric Botcazou wrote:

> > Do you have a reason for using fp-bit instead of soft-fp?
> 
> Apart from the obvious historical reason, probably not, but recently added 
> ports (Blackfin, Epiphany) also use it so I'm not sure we want to change it.

I doubt they have any good reason for using it.

> > libgcc files are generally GPL+exception, not LGPL without exception with
> > a very old FSF address (config/visium/div64.c, mod64.c,
> > set_trampoline_parity.c, udiv64.c, udivmod64.c, umod64.c)
> 
> Files whose copyright/origin is clear are already GPL+exception, but these 6 
> files were originally imported from Glibc so they aren't in the same basket.
> 
> I guess I can reuse the copyright notice of soft-fp for them.

Well, you'll need FSF approval to relicense - and unless you want to keep 
the same sources used verbatim in both places, the GPL+exception notice is 
the obvious one given such approval.  (But in any case, putting in LGPL 
files without a license exception seems a bad idea, because it goes 
against the standard message about building your program with GCC not 
imposing restrictions on distribution of the resulting binary.)

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH 3/4] Add Visium support to gcc

[Joseph Myers]

On Mon, 15 Dec 2014, Eric Botcazou wrote:

> > (and you should verify that the port builds cleanly with --enable-werror
> > -always, for both 32-bit and 64-bit hosts, when building using current trunk 
> > GCC).
> 
> Do you mean a bootstrap of the cross-compiler with --enable-werror-always on a 
> 32-bit and a 64-bit host?  OK, I'll do that.

First, bootstrap a native compiler from current trunk.  Then, use that 
native compiler to build the cross compiler configured with 
--enable-werror-always.  (--enable-werror-always is only expected to work 
when GCC is being built with the same version of GCC, as the compiler may 
not be -Werror-clean when built with other versions.)  Do this for both 
32-bit and 64-bit hosts.

For a cross-compiler, doing this provides equivalent -Werror coverage to 
what simple bootstrap does for a native compiler.

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH 2/4] Add Visium support to libgcc

[Eric Botcazou]

> Well, you'll need FSF approval to relicense - and unless you want to keep
> the same sources used verbatim in both places, the GPL+exception notice is
> the obvious one given such approval.  (But in any case, putting in LGPL
> files without a license exception seems a bad idea, because it goes
> against the standard message about building your program with GCC not
> imposing restrictions on distribution of the resulting binary.)

OK, I'm going to reimplement it based on libgcc2.c then.

-- 
Eric Botcazou

Re: [PATCH 2/4] Add Visium support to libgcc

[Eric Botcazou]

[-- Attachment #1: Type: text/plain, Size: 330 bytes --]

Revision version, the divmod and the parity routines have been reimplemented 
based on libgcc2.c and all the new files are now under GPL+exception.


libgcc/ChangeLog

2014-12-19  Eric Botcazou  <ebotcazou@adacore.com>
        
        * config.host: Add Visium support.
        * config/visium: New directory.


-- 
Eric Botcazou

[-- Attachment #2: libgcc_visium-2.tar.gz --]
[-- Type: application/x-compressed-tar, Size: 6129 bytes --]

[-- Attachment #3: p2.diff --]
[-- Type: text/x-patch, Size: 431 bytes --]

Index: config.host
===================================================================
--- config.host	(revision 218617)
+++ config.host	(working copy)
@@ -1233,6 +1233,10 @@ vax-*-netbsdelf*)
 	;;
 vax-*-openbsd*)
 	;;
+visium-*-elf*)
+        extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+        tmake_file="visium/t-visium t-fdpbit"
+        ;;
 xstormy16-*-elf)
 	tmake_file="stormy16/t-stormy16 t-fdpbit"
 	;;

Re: [PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

> First, bootstrap a native compiler from current trunk.  Then, use that
> native compiler to build the cross compiler configured with
> --enable-werror-always.  (--enable-werror-always is only expected to work
> when GCC is being built with the same version of GCC, as the compiler may
> not be -Werror-clean when built with other versions.)  Do this for both
> 32-bit and 64-bit hosts.

Done, no changes required.

-- 
Eric Botcazou

Re: [PATCH 4/4] Add Visium support to gcc/testsuite

[Jeff Law]

On 12/11/14 17:13, Eric Botcazou wrote:
> gcc/testsuite/ChangeLog:
>
> 2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>
>
> 	* lib/target-supports.exp (check_profiling_available): Return 0 for
> 	Visium.
> 	(check_effective_target_tls_runtime): Likewise.
> 	(check_effective_target_logical_op_short_circuit): Return 1 for Visium.
> 	* gcc.dg/20020312-2.c: Adjust for Visium.
> 	* gcc.dg/tls/thr-cse-1.c: Likewise
> 	* gcc.dg/tree-ssa/20040204-1.c: Likewise
> 	* gcc.dg/tree-ssa/loop-1.c: Likewise.
> 	* gcc.dg/weak/typeof-2.c: Likewise.
OK when rest of port is OK'd.

Jeff

Re: [PATCH 1/4] Add Visium support to toplevel

[Jeff Law]

On 12/11/14 17:09, Eric Botcazou wrote:
> ChangeLog
>
> 2014-12-11  Eric Botcazou  <ebotcazou@adacore.com>
>
> 	* config.sub: Update from upstream config repo.
> 	* configure.ac: Add Visium support.
> 	* configure: Regenerate.
OK when rest of bits are approved.

jeff

Re: [PATCH 2/4] Add Visium support to libgcc

[Jeff Law]

On 12/19/14 15:33, Eric Botcazou wrote:
> Revision version, the divmod and the parity routines have been reimplemented
> based on libgcc2.c and all the new files are now under GPL+exception.
>
>
> libgcc/ChangeLog
>
> 2014-12-19  Eric Botcazou  <ebotcazou@adacore.com>
>
>          * config.host: Add Visium support.
>          * config/visium: New directory.
OK when rest of port is approved.

jeff

Re: [PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

[-- Attachment #1: Type: text/plain, Size: 502 bytes --]

Revised version after Joseph's comments and latest libgcc changes.


gcc/ChangeLog

2014-12-22  Eric Botcazou  <ebotcazou@adacore.com>

	* config.gcc: Add Visium support.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* doc/extend.texi (interrupt attribute): Add Visium.
	* doc/invoke.texi: Document Visium options.
	* doc/install.texi: Document Visium target.
	* doc/md.texi: Document Visium constraints.
	* common/config/visium: New directory.
	* config/visium: Likewise.



-- 
Eric Botcazou

[-- Attachment #2: gcc_visium-2.tar.gz --]
[-- Type: application/x-compressed-tar, Size: 69834 bytes --]

[-- Attachment #3: p3.diff --]
[-- Type: text/x-patch, Size: 9035 bytes --]

Index: config.gcc
===================================================================
--- config.gcc	(revision 218987)
+++ config.gcc	(working copy)
@@ -2888,6 +2888,10 @@ vax-*-openbsd*)
 	extra_options="${extra_options} openbsd.opt"
 	use_collect2=yes
 	;;
+visium-*-elf*)
+	tm_file="dbxelf.h elfos.h ${tm_file} visium/elf.h newlib-stdint.h"
+	tmake_file="visium/t-visium visium/t-crtstuff"
+	;;
 xstormy16-*-elf)
 	# For historical reasons, the target files omit the 'x'.
 	tm_file="dbxelf.h elfos.h newlib-stdint.h stormy16/stormy16.h"
Index: configure.ac
===================================================================
--- configure.ac	(revision 218987)
+++ configure.ac	(working copy)
@@ -4442,7 +4442,7 @@ esac
 case "$cpu_type" in
   aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
   | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
-  | xstormy16 | xtensa)
+  | visium | xstormy16 | xtensa)
     insn="nop"
     ;;
   ia64 | s390)
Index: doc/extend.texi
===================================================================
--- doc/extend.texi	(revision 218987)
+++ doc/extend.texi	(working copy)
@@ -2935,12 +2935,11 @@ least version 2.20.1), and GNU C library
 @item interrupt
 @cindex interrupt handler functions
 Use this attribute on the ARC, ARM, AVR, CR16, Epiphany, M32C, M32R/D,
-m68k, MeP, MIPS, MSP430, RL78, RX and Xstormy16 ports to indicate that
-the specified function is an
-interrupt handler.  The compiler generates function entry and exit
-sequences suitable for use in an interrupt handler when this attribute
-is present.  With Epiphany targets it may also generate a special section with
-code to initialize the interrupt vector table.
+m68k, MeP, MIPS, MSP430, RL78, RX, Visium and Xstormy16 ports to indicate
+that the specified function is an interrupt handler.  The compiler generates
+function entry and exit sequences suitable for use in an interrupt handler
+when this attribute is present.  With Epiphany targets it may also generate
+a special section with code to initialize the interrupt vector table.
 
 Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
 and SH processors can be specified via the @code{interrupt_handler} attribute.
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi	(revision 218987)
+++ doc/invoke.texi	(working copy)
@@ -1064,6 +1064,10 @@ See RS/6000 and PowerPC Options.
 @emph{VAX Options}
 @gccoptlist{-mg  -mgnu  -munix}
 
+@emph{Visium Options}
+@gccoptlist{-mdebug -msim -mfpu -mno-fpu -mhard-float -msoft-float @gol
+-mcpu=@var{cpu-type} -mtune=@var{cpu-type} -msv-mode -muser-mode}
+
 @emph{VMS Options}
 @gccoptlist{-mvms-return-codes -mdebug-main=@var{prefix} -mmalloc64 @gol
 -mpointer-size=@var{size}}
@@ -11892,6 +11896,7 @@ platform.
 * TILEPro Options::
 * V850 Options::
 * VAX Options::
+* Visium Options::
 * VMS Options::
 * VxWorks Options::
 * x86-64 Options::
@@ -22532,6 +22537,77 @@ GNU assembler is being used.
 Output code for G-format floating-point numbers instead of D-format.
 @end table
 
+@node Visium Options
+@subsection Visium Options
+@cindex Visium options
+
+@table @gcctabopt
+
+@item -mdebug
+@opindex mdebug
+A program which performs file I/O and is destined to run on an MCM target
+should be linked with this option.  It causes the libraries libc.a and
+libdebug.a to be linked.  The program should be run on the target under
+the control of the GDB remote debugging stub.
+
+@item -msim
+@opindex msim
+A program which performs file I/O and is destined to run on the simulator
+should be linked with option.  This causes libraries libc.a and libsim.a to
+be linked.
+
+@item -mfpu
+@itemx -mhard-float
+@opindex mfpu
+@opindex mhard-float
+Generate code containing floating-point instructions.  This is the
+default.
+
+@item -mno-fpu
+@itemx -msoft-float
+@opindex mno-fpu
+@opindex msoft-float
+Generate code containing library calls for floating-point.
+
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option.  In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
+
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type @var{cpu_type}.  Supported values for @var{cpu_type} are
+@samp{mcm}, @samp{gr5} and @samp{gr6}.
+
+@samp{mcm} is a synonym of @samp{gr5} present for backward compatibility.
+
+By default (unless configured otherwise), GCC generates code for the GR5
+variant of the Visium architecture.  
+
+With @option{-mcpu=gr6}, GCC generates code for the GR6 variant of the Visium
+architecture.  The only difference from GR5 code is that the compiler will
+generate block move instructions.
+
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type @var{cpu_type},
+but do not set the instruction set or register set that the option
+@option{-mcpu=@var{cpu_type}} would.
+
+@item -msv-mode
+@opindex msv-mode
+Generate code for the supervisor mode, where there are no restrictions on
+the access to general registers.  This is the default.
+
+@item -muser-mode
+@opindex muser-mode
+Generate code for the user mode, where the access to some general registers
+is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
+mode; on the GR6, only registers r29 to r31 are affected.
+@end table
+
 @node VMS Options
 @subsection VMS Options
 
Index: doc/md.texi
===================================================================
--- doc/md.texi	(revision 218987)
+++ doc/md.texi	(working copy)
@@ -3972,6 +3972,56 @@ A 2-element vector constant with identic
 
 @end table
 
+@item Visium---@file{config/visium/constraints.md}
+@table @code
+@item b
+EAM register @code{mdb}
+
+@item c
+EAM register @code{mdc}
+
+@item f
+Floating point register
+
+@ifset INTERNALS
+@item k
+Register for sibcall optimization
+@end ifset
+
+@item l
+General register, but not @code{r29}, @code{r30} and @code{r31}
+
+@item t
+Register @code{r1}
+
+@item u
+Register @code{r2}
+
+@item v
+Register @code{r3}
+
+@item G
+Floating-point constant 0.0
+
+@item J
+Integer constant in the range 0 .. 65535 (16-bit immediate)
+
+@item K
+Integer constant in the range 1 .. 31 (5-bit immediate)
+
+@item L
+Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
+
+@item M
+Integer constant @minus{}1
+
+@item O
+Integer constant 0
+
+@item P
+Integer constant 32
+@end table
+
 @item Xtensa---@file{config/xtensa/constraints.md}
 @table @code
 @item a
Index: doc/install.texi
===================================================================
--- doc/install.texi	(revision 218987)
+++ doc/install.texi	(working copy)
@@ -3349,6 +3349,8 @@ information have to.
 @item
 @uref{#tilepro-x-linux,,tilepro-*-linux*}
 @item
+@uref{#visium-x-elf, visium-*-elf}
+@item
 @uref{#x-x-vxworks,,*-*-vxworks*}
 @item
 @uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
@@ -4649,6 +4651,14 @@ binutils-2.22 or newer.
 
 @html
 <hr />
+@end html
+@anchor{visium-x-elf}
+@heading visium-*-elf
+CDS VISIUMcore processor.
+This configuration is intended for embedded systems.
+
+@html
+<hr />
 @end html
 @anchor{x-x-vxworks}
 @heading *-*-vxworks*
Index: common/config/visium/visium-common.c
===================================================================
--- common/config/visium/visium-common.c	(revision 0)
+++ common/config/visium/visium-common.c	(revision 0)
@@ -0,0 +1,38 @@
+/* Common hooks for Visium.
+   Copyright (C) 2002-2014 Free Software Foundation, Inc.
+   Contributed by C.Nettleton,J.P.Parkes and P.Garbett.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+
+/* Set default optimization options.  */
+static const struct default_options visium_option_optimization_table[] =
+  {
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
+  };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE visium_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

Re: [PATCH 3/4] Add Visium support to gcc

[Jeff Law]

On 12/22/14 04:14, Eric Botcazou wrote:
> Revised version after Joseph's comments and latest libgcc changes.
>
>
> gcc/ChangeLog
>
> 2014-12-22  Eric Botcazou  <ebotcazou@adacore.com>
>
> 	* config.gcc: Add Visium support.
> 	* configure.ac: Likewise.
> 	* configure: Regenerate.
> 	* doc/extend.texi (interrupt attribute): Add Visium.
> 	* doc/invoke.texi: Document Visium options.
> 	* doc/install.texi: Document Visium target.
> 	* doc/md.texi: Document Visium constraints.
> 	* common/config/visium: New directory.
> 	* config/visium: Likewise.
I don't see anything particularly offensive.  Actually it looks like a 
reasonably clean RISC port.

I'm a little concerned about the MODES_TIEABLE_P definition, but if it's 
working, I wouldn't mess with it.

Any thoughts on using LRA for this port?  Ideally we want to be moving 
away from reload as much as we can.

I didn't look closely, do you need blockage insns in your epilogue/prologue?

For the prologue, if you store callee saved registers using the frame 
pointer, then you need a blockage to ensure those stores don't bubble up 
before the local stack gets allocated.  And you need something analogous 
in the epilogue.  I didn't check your port carefully for this, but I'd 
advise doing so.

Presumably you're going to be the maintainer for this port?  If not you, 
then who will maintain the port (so i can get maintainership officially 
blessed by the SC).

I think this is good to go into the trunk.  The blockage issue (if it's 
an issue) can be resolved as a follow-up.

Jeff

Re: [PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

> I don't see anything particularly offensive.  Actually it looks like a
> reasonably clean RISC port.

Thanks for the review.

> I'm a little concerned about the MODES_TIEABLE_P definition, but if it's
> working, I wouldn't mess with it.

Could you elaborate?  Do you find it too restrictive?

> Any thoughts on using LRA for this port?  Ideally we want to be moving
> away from reload as much as we can.

I can only promise to start experimenting with it and report issues, if any.
The port is quite mature and the performances are closely monitored so bold 
changes need to be made with extra caution.

> I didn't look closely, do you need blockage insns in your epilogue/prologue?

No, I don't think so.

> For the prologue, if you store callee saved registers using the frame
> pointer, then you need a blockage to ensure those stores don't bubble up
> before the local stack gets allocated.  And you need something analogous
> in the epilogue.  I didn't check your port carefully for this, but I'd
> advise doing so.

The register saves in the prologue are based on the stack pointer because the 
frame pointer is established only at the very end and its value comprises the 
allocation.  The restores in the epilogue are also based on the stack pointer 
and the stack_restore and stack_pop patterns which do the deallocation have an 
explicit memory barrier.

> Presumably you're going to be the maintainer for this port?

Yes, I'm going to be the maintainer for now.

> I think this is good to go into the trunk.  The blockage issue (if it's
> an issue) can be resolved as a follow-up.

OK, thanks again.

-- 
Eric Botcazou

Re: [PATCH 3/4] Add Visium support to gcc

[Jeff Law]

On 01/03/15 08:16, Eric Botcazou wrote:
>
>> I'm a little concerned about the MODES_TIEABLE_P definition, but if it's
>> working, I wouldn't mess with it.
>
> Could you elaborate?  Do you find it too restrictive?
I'm a little concerned it's too loose.  Basically it says that if both 
modes are integer modes, then they're tieable.  However, 
HARD_REGNO_MODE_OK may return different values for MODE1 and MODE2, even 
if both are integer modes.

My recollection is if MODES_TIEABLE_P returns true for mode1 and mode2, 
then HARD_REGNO_MODE_OK must return the same value when passed mode1 and 
mode2 regardless of the hard register and it's not obvious if 
HARD_REGNO_MODE_OK fits that criteria for this port.

Looking at the current docs, the language has been watered down from my 
recollection.  So.....

If it's working, then I'd leave it as-is.


>
>> Any thoughts on using LRA for this port?  Ideally we want to be moving
>> away from reload as much as we can.
>
> I can only promise to start experimenting with it and report issues, if any.
> The port is quite mature and the performances are closely monitored so bold
> changes need to be made with extra caution.
Understood.

FWIW, I suspect this is the last port I'll approve that doesn't use LRA 
instead of reload.


>
> Yes, I'm going to be the maintainer for now.
Given you're already maintaining other parts of GCC, I really just 
consider appointing you as the maintainer for the port a formality. 
I'll start that process, but go ahead and list yourself as the 
maintainer in the MAINTAINERS file.

jeff

Re: [PATCH 3/4] Add Visium support to gcc

[Eric Botcazou]

> I'm a little concerned it's too loose.  Basically it says that if both
> modes are integer modes, then they're tieable.  However,
> HARD_REGNO_MODE_OK may return different values for MODE1 and MODE2, even
> if both are integer modes.
> 
> My recollection is if MODES_TIEABLE_P returns true for mode1 and mode2,
> then HARD_REGNO_MODE_OK must return the same value when passed mode1 and
> mode2 regardless of the hard register and it's not obvious if
> HARD_REGNO_MODE_OK fits that criteria for this port.

I see, thanks for explaining.  I didn't write these macros and I agree that 
HARD_REGNO_MODE_OK is a little convoluted, but MODES_TIEABLE_P is correct as 
far as the arch is concerned so I'd rather tweak the former if need be.

> Given you're already maintaining other parts of GCC, I really just
> consider appointing you as the maintainer for the port a formality.
> I'll start that process, but go ahead and list yourself as the
> maintainer in the MAINTAINERS file.

Will do.

-- 
Eric Botcazou