From: "Kewen.Lin" <linkw@linux.ibm.com>
To: Jakub Jelinek <jakub@redhat.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Richard Biener <richard.guenther@gmail.com>,
richard.sandiford@arm.com,
Segher Boessenkool <segher@kernel.crashing.org>,
Bill Schmidt <wschmidt@linux.ibm.com>
Subject: Re: [PATCH, rs6000] Support vrotr<mode>3 for int vector types
Date: Wed, 17 Jul 2019 09:38:00 -0000 [thread overview]
Message-ID: <3a4d20e2-a586-a957-0baf-92f2ef4f7a8a@linux.ibm.com> (raw)
In-Reply-To: <20190717084211.GC2125@tucnak>
on 2019/7/17 脧脗脦莽4:42, Jakub Jelinek wrote:
> On Wed, Jul 17, 2019 at 04:32:15PM +0800, Kewen.Lin wrote:
>> --- a/gcc/config/rs6000/vector.md
>> +++ b/gcc/config/rs6000/vector.md
>> @@ -1260,6 +1260,32 @@
>> "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
>> "")
>>
>> +;; Expanders for rotatert to make use of vrotl
>> +(define_expand "vrotr<mode>3"
>> + [(set (match_operand:VEC_I 0 "vint_operand")
>> + (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand")
>> + (match_operand:VEC_I 2 "vint_reg_or_const_vector")))]
>> + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
>> +{
>> + machine_mode inner_mode = GET_MODE_INNER (<MODE>mode);
>> + unsigned int bits = GET_MODE_PRECISION (inner_mode);
>> + rtx imm_vec = gen_const_vec_duplicate (<MODE>mode, GEN_INT (bits));
>> + rtx rot_count = gen_reg_rtx (<MODE>mode);
>> + if (GET_CODE (operands[2]) == CONST_VECTOR)
>> + {
>> + imm_vec = simplify_const_binary_operation (MINUS, <MODE>mode, imm_vec,
>> + operands[2]);
>> + rot_count = force_reg (<MODE>mode, imm_vec);
>> + }
>> + else
>> + {
>> + rtx imm_reg = force_reg (<MODE>mode, imm_vec);
>> + emit_insn (gen_sub<mode>3 (rot_count, imm_reg, operands[2]));
>> + }
>
> Is this actually correct if one or more elements in operands[2] are 0?
> If vrotl<mode>3 acts with truncated shift count, that is not an issue
> (but then perhaps you wouldn't have to compute imm_reg - operands[2] but
> just - operands[2]), but if it does something else, then prec - 0 will be
> prec and thus outside of the allowed rotate count. Or does rs6000 allow
> rotate counts to be 0 to prec inclusive?
>
> Jakub
>
Hi Jakub,
Good question, the vector rotation for byte looks like (others are similar):
vrlb VRT,VRA,VRB
do i=0 to 127 by 8
sh = (VRB)[i+5:i+7]
VRT[i:i+7] = (VRA)[i:i+7] <<< sh
end
It only takes care of the counts from 0 to prec-1 (inclusive) [log2(prec) bits]
So it's fine even operands[2] are zero or negative.
Take byte as example, prec is 8.
- rot count is 0, then minus res gets 8. (out of 3 bits range), same as 0.
- rot count is 9, then minus res gets -1. (3 bits parsed as 7), the original
rot count 9 was parsed as 1 (in 3 bits range).
- rot count is -1, then minus res gets 9, (3 bits parsed as 1), the original
rot count was parsed as 7 (in 3 bits range).
It's a good idea to just use negate! Thanks!!
Kewen
next prev parent reply other threads:[~2019-07-17 9:23 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-15 8:59 Check rrotate optab first when transforming lrotate Kewen.Lin
2019-07-15 9:16 ` Jakub Jelinek
2019-07-15 9:19 ` Richard Biener
2019-07-15 9:20 ` Richard Sandiford
2019-07-15 10:54 ` Kewen.Lin
2019-07-15 14:51 ` Segher Boessenkool
[not found] ` <d2ccc831-c805-c7b8-5a90-cb3e5ee5ed8b@linux.ibm.com>
2019-07-16 8:48 ` [RFC] Consider lrotate const rotation in vectorizer Kewen.Lin
2019-07-17 8:42 ` [PATCH, rs6000] Support vrotr<mode>3 for int vector types Kewen.Lin
2019-07-17 8:44 ` Jakub Jelinek
2019-07-17 9:38 ` Kewen.Lin [this message]
2019-07-17 10:18 ` Jakub Jelinek
2019-07-17 13:48 ` Segher Boessenkool
2019-07-18 6:06 ` Kewen.Lin
2019-07-18 20:06 ` Segher Boessenkool
2019-07-19 6:51 ` Kewen.Lin
2019-07-19 15:49 ` Segher Boessenkool
2019-07-23 7:32 ` [PATCH V2, " Kewen.Lin
2019-07-25 14:24 ` Segher Boessenkool
2019-07-26 3:33 ` [PATCH V3, " Kewen.Lin
2019-07-26 3:37 ` [PATCH V4, " Kewen.Lin
2019-07-26 14:28 ` [PATCH V3, " Segher Boessenkool
2019-08-02 8:59 ` [PATCH V5, " Kewen.Lin
2019-08-03 20:52 ` Segher Boessenkool
2019-08-05 3:41 ` Kewen.Lin
2019-08-05 21:50 ` Segher Boessenkool
2019-08-06 3:11 ` Kewen.Lin
2019-08-06 15:12 ` Segher Boessenkool
2019-07-17 10:39 ` [RFC] Consider lrotate const rotation in vectorizer Richard Biener
2019-07-17 11:19 ` Jakub Jelinek
2019-07-17 11:35 ` Richard Biener
2019-07-17 11:56 ` Richard Biener
2019-07-17 13:58 ` Segher Boessenkool
2019-07-17 17:51 ` Segher Boessenkool
2019-07-18 7:03 ` Jakub Jelinek
2019-07-18 19:45 ` Segher Boessenkool
2019-07-18 15:17 ` Richard Earnshaw (lists)
2019-07-18 15:26 ` Jakub Jelinek
2019-07-18 15:31 ` Richard Earnshaw (lists)
2019-07-18 15:35 ` Jakub Jelinek
2019-07-18 15:44 ` Richard Earnshaw (lists)
2019-07-18 18:04 ` Segher Boessenkool
2019-07-18 6:28 ` Kewen.Lin
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