From: will schmidt <will_schmidt@vnet.ibm.com>
To: Bill Schmidt <wschmidt@linux.ibm.com>, gcc-patches@gcc.gnu.org
Cc: segher@kernel.crashing.org
Subject: Re: [PATCH 47/55] rs6000: Builtin expansion, part 4
Date: Tue, 27 Jul 2021 16:06:49 -0500 [thread overview]
Message-ID: <3b98c985191f7d3d0be8ab19e6580887991c4d74.camel@vnet.ibm.com> (raw)
In-Reply-To: <1f28ba77c244256484e000eab60d041181612ff4.1623941442.git.wschmidt@linux.ibm.com>
On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> 2021-03-05 Bill Schmidt <wschmidt@linux.ibm.com>
>
Hi,
> gcc/
> * config/rs6000/rs6000-call.c (elemrev_icode): Implement.
> (ldv_expand_builtin): Likewise.
> (lxvrse_expand_builtin): Likewise.
> (lxvrze_expand_builtin): Likewise.
> (stv_expand_builtin): Likewise.
> ---
> gcc/config/rs6000/rs6000-call.c | 217 ++++++++++++++++++++++++++++++++
> 1 file changed, 217 insertions(+)
>
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index ad3e6a4bbe5..981eabc1187 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -14710,12 +14710,114 @@ new_cpu_expand_builtin (enum rs6000_gen_builtins fcode,
> static insn_code
> elemrev_icode (rs6000_gen_builtins fcode)
> {
> + switch (fcode)
> + {
> + default:
> + gcc_unreachable ();
> + case RS6000_BIF_ST_ELEMREV_V1TI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
> + : CODE_FOR_vsx_st_elemrev_v1ti);
Hmm, would it be worthy to rename one of the pair so they both match "_st_" or "_store_" ?
CODE_FOR_vsx_store_v1ti
CODE_FOR_vsx_st_elemrev_v1ti
Same for _ld_ and _load_ , but it's all a conversation for elsewhere... :-)
Ok,
> + case RS6000_BIF_ST_ELEMREV_V2DF:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
> + : CODE_FOR_vsx_st_elemrev_v2df);
> + case RS6000_BIF_ST_ELEMREV_V2DI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
> + : CODE_FOR_vsx_st_elemrev_v2di);
> + case RS6000_BIF_ST_ELEMREV_V4SF:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
> + : CODE_FOR_vsx_st_elemrev_v4sf);
> + case RS6000_BIF_ST_ELEMREV_V4SI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
> + : CODE_FOR_vsx_st_elemrev_v4si);
> + case RS6000_BIF_ST_ELEMREV_V8HI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
> + : CODE_FOR_vsx_st_elemrev_v8hi);
> + case RS6000_BIF_ST_ELEMREV_V16QI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
> + : CODE_FOR_vsx_st_elemrev_v16qi);
> + case RS6000_BIF_LD_ELEMREV_V2DF:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
> + : CODE_FOR_vsx_ld_elemrev_v2df);
> + case RS6000_BIF_LD_ELEMREV_V1TI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
> + : CODE_FOR_vsx_ld_elemrev_v1ti);
> + case RS6000_BIF_LD_ELEMREV_V2DI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
> + : CODE_FOR_vsx_ld_elemrev_v2di);
> + case RS6000_BIF_LD_ELEMREV_V4SF:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
> + : CODE_FOR_vsx_ld_elemrev_v4sf);
> + case RS6000_BIF_LD_ELEMREV_V4SI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
> + : CODE_FOR_vsx_ld_elemrev_v4si);
> + case RS6000_BIF_LD_ELEMREV_V8HI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
> + : CODE_FOR_vsx_ld_elemrev_v8hi);
> + case RS6000_BIF_LD_ELEMREV_V16QI:
> + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
> + : CODE_FOR_vsx_ld_elemrev_v16qi);
> + }
> + gcc_unreachable ();
> return (insn_code) 0;
> }
ok
> static rtx
> ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode)
> {
> + rtx pat, addr;
> + bool blk = (icode == CODE_FOR_altivec_lvlx
> + || icode == CODE_FOR_altivec_lvlxl
> + || icode == CODE_FOR_altivec_lvrx
> + || icode == CODE_FOR_altivec_lvrxl);
> +
> + if (target == 0
> + || GET_MODE (target) != tmode
> + || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
No space after "!" ? (here and later on 'pat'.).
> + target = gen_reg_rtx (tmode);
> +
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> +
> + /* For LVX, express the RTL accurately by ANDing the address with -16.
> + LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
> + so the raw address is fine. */
good comment. :-)
> + if (icode == CODE_FOR_altivec_lvx_v1ti
> + || icode == CODE_FOR_altivec_lvx_v2df
> + || icode == CODE_FOR_altivec_lvx_v2di
> + || icode == CODE_FOR_altivec_lvx_v4sf
> + || icode == CODE_FOR_altivec_lvx_v4si
> + || icode == CODE_FOR_altivec_lvx_v8hi
> + || icode == CODE_FOR_altivec_lvx_v16qi)
> + {
> + rtx rawaddr;
> + if (op[0] == const0_rtx)
> + rawaddr = op[1];
> + else
> + {
> + op[0] = copy_to_mode_reg (Pmode, op[0]);
> + rawaddr = gen_rtx_PLUS (Pmode, op[1], op[0]);
> + }
> + addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
> + addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
> +
> + emit_insn (gen_rtx_SET (target, addr));
> + }
> + else
> + {
> + if (op[0] == const0_rtx)
> + addr = gen_rtx_MEM (blk ? BLKmode : tmode, op[1]);
> + else
> + {
> + op[0] = copy_to_mode_reg (Pmode, op[0]);
> + addr = gen_rtx_MEM (blk ? BLKmode : tmode,
> + gen_rtx_PLUS (Pmode, op[1], op[0]));
> + }
> +
> + pat = GEN_FCN (icode) (target, addr);
> + if (! pat)
> + return 0;
> + emit_insn (pat);
> + }
> +
> return target;
> }
>
> @@ -14723,6 +14825,42 @@ static rtx
> lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op,
> machine_mode tmode, machine_mode smode)
> {
> + rtx pat, addr;
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> +
> + if (op[0] == const0_rtx)
> + addr = gen_rtx_MEM (tmode, op[1]);
> + else
> + {
> + op[0] = copy_to_mode_reg (Pmode, op[0]);
> + addr = gen_rtx_MEM (smode,
> + gen_rtx_PLUS (Pmode, op[1], op[0]));
> + }
> +
> + rtx discratch = gen_reg_rtx (DImode);
> + rtx tiscratch = gen_reg_rtx (TImode);
> +
> + /* Emit the lxvr*x insn. */
> + pat = GEN_FCN (icode) (tiscratch, addr);
> + if (!pat)
> + return 0;
> + emit_insn (pat);
> +
> + /* Emit a sign extension from QI,HI,WI to double (DI). */
> + rtx scratch = gen_lowpart (smode, tiscratch);
> + if (icode == CODE_FOR_vsx_lxvrbx)
> + emit_insn (gen_extendqidi2 (discratch, scratch));
> + else if (icode == CODE_FOR_vsx_lxvrhx)
> + emit_insn (gen_extendhidi2 (discratch, scratch));
> + else if (icode == CODE_FOR_vsx_lxvrwx)
> + emit_insn (gen_extendsidi2 (discratch, scratch));
> + /* Assign discratch directly if scratch is already DI. */
> + if (icode == CODE_FOR_vsx_lxvrdx)
> + discratch = scratch;
> +
> + /* Emit the sign extension from DI (double) to TI (quad). */
> + emit_insn (gen_extendditi2 (target, discratch));
> +
Ok.
>
> return target;
> }
>
> @@ -14730,6 +14868,22 @@ static rtx
> lxvrze_expand_builtin (rtx target, insn_code icode, rtx *op,
> machine_mode tmode, machine_mode smode)
> {
> + rtx pat, addr;
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> +
> + if (op[0] == const0_rtx)
> + addr = gen_rtx_MEM (tmode, op[1]);
> + else
> + {
> + op[0] = copy_to_mode_reg (Pmode, op[0]);
> + addr = gen_rtx_MEM (smode,
> + gen_rtx_PLUS (Pmode, op[1], op[0]));
> + }
> +
> + pat = GEN_FCN (icode) (target, addr);
> + if (!pat)
> + return 0;
> + emit_insn (pat);
Ok
> return target;
> }
>
> @@ -14737,6 +14891,69 @@ static rtx
> stv_expand_builtin (insn_code icode, rtx *op,
> machine_mode tmode, machine_mode smode)
> {
> + rtx pat, addr, rawaddr, truncrtx;
> + op[2] = copy_to_mode_reg (Pmode, op[2]);
> +
> + /* For STVX, express the RTL accurately by ANDing the address with -16.
> + STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
> + so the raw address is fine. */
> + if (icode == CODE_FOR_altivec_stvx_v2df
> + || icode == CODE_FOR_altivec_stvx_v2di
> + || icode == CODE_FOR_altivec_stvx_v4sf
> + || icode == CODE_FOR_altivec_stvx_v4si
> + || icode == CODE_FOR_altivec_stvx_v8hi
> + || icode == CODE_FOR_altivec_stvx_v16qi)
> + {
> + if (op[1] == const0_rtx)
> + rawaddr = op[2];
> + else
> + {
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> + rawaddr = gen_rtx_PLUS (Pmode, op[2], op[1]);
> + }
> +
> + addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
> + addr = gen_rtx_MEM (tmode, addr);
> + op[0] = copy_to_mode_reg (tmode, op[0]);
> + emit_insn (gen_rtx_SET (addr, op[0]));
> + }
> + else if (icode == CODE_FOR_vsx_stxvrbx
> + || icode == CODE_FOR_vsx_stxvrhx
> + || icode == CODE_FOR_vsx_stxvrwx
> + || icode == CODE_FOR_vsx_stxvrdx)
> + {
> + truncrtx = gen_rtx_TRUNCATE (tmode, op[0]);
> + op[0] = copy_to_mode_reg (E_TImode, truncrtx);
> +
> + if (op[1] == const0_rtx)
> + addr = gen_rtx_MEM (Pmode, op[2]);
> + else
> + {
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
> + }
> + pat = GEN_FCN (icode) (addr, op[0]);
> + if (pat)
> + emit_insn (pat);
> + }
> + else
> + {
> + if (! (*insn_data[icode].operand[1].predicate) (op[0], smode))
> + op[0] = copy_to_mode_reg (smode, op[0]);
> +
> + if (op[1] == const0_rtx)
> + addr = gen_rtx_MEM (tmode, op[2]);
> + else
> + {
> + op[1] = copy_to_mode_reg (Pmode, op[1]);
> + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
> + }
> +
> + pat = GEN_FCN (icode) (addr, op[0]);
> + if (pat)
> + emit_insn (pat);
> + }
> +
Ok
lgtm,
thanks
-Will
> return NULL_RTX;
> }
>
next prev parent reply other threads:[~2021-07-27 21:07 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 15:18 [PATCHv3 00/55] Replace the Power target-specific builtin machinery Bill Schmidt
2021-06-17 15:18 ` [PATCH 01/55] Support scanning of build-time GC roots in gengtype Bill Schmidt
2021-06-17 15:18 ` [PATCH 02/55] rs6000: Initial create of rs6000-gen-builtins.c Bill Schmidt
2021-06-17 15:18 ` [PATCH 03/55] rs6000: Add initial input files Bill Schmidt
2021-06-17 15:18 ` [PATCH 04/55] rs6000: Add file support and functions for diagnostic support Bill Schmidt
2021-06-17 15:18 ` [PATCH 05/55] rs6000: Add helper functions for parsing Bill Schmidt
2021-07-09 19:32 ` will schmidt
2021-07-14 22:58 ` Segher Boessenkool
2021-07-14 23:32 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 06/55] rs6000: Add functions for matching types, part 1 of 3 Bill Schmidt
2021-06-17 15:18 ` [PATCH 07/55] rs6000: Add functions for matching types, part 2 " Bill Schmidt
2021-06-17 15:18 ` [PATCH 08/55] rs6000: Add functions for matching types, part 3 " Bill Schmidt
2021-06-17 15:18 ` [PATCH 09/55] rs6000: Red-black tree implementation for balanced tree search Bill Schmidt
2021-06-17 15:18 ` [PATCH 10/55] rs6000: Main function with stubs for parsing and output Bill Schmidt
2021-07-19 19:15 ` Segher Boessenkool
2021-07-20 22:19 ` Bill Schmidt
2021-07-20 23:22 ` Segher Boessenkool
2021-07-21 1:51 ` Bill Schmidt
2021-07-21 15:43 ` Segher Boessenkool
2021-07-21 16:08 ` Bill Schmidt
2021-07-21 16:16 ` Bill Schmidt
2021-06-17 15:18 ` [PATCH 11/55] rs6000: Parsing built-in input file, part 1 of 3 Bill Schmidt
2021-07-19 20:39 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 12/55] rs6000: Parsing built-in input file, part 2 " Bill Schmidt
2021-07-19 22:07 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 13/55] rs6000: Parsing built-in input file, part 3 " Bill Schmidt
2021-07-19 22:13 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 14/55] rs6000: Parsing of overload input file Bill Schmidt
2021-07-19 23:09 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 15/55] rs6000: Build and store function type identifiers Bill Schmidt
2021-07-20 0:04 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 16/55] rs6000: Write output to the builtin definition include file Bill Schmidt
2021-07-20 23:27 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 17/55] rs6000: Write output to the builtins header file Bill Schmidt
2021-07-20 23:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 18/55] rs6000: Write output to the builtins init file, part 1 of 3 Bill Schmidt
2021-07-20 23:51 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 19/55] rs6000: Write output to the builtins init file, part 2 " Bill Schmidt
2021-07-20 23:53 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 20/55] rs6000: Write output to the builtins init file, part 3 " Bill Schmidt
2021-07-21 17:08 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 21/55] rs6000: Write static initializations for built-in table Bill Schmidt
2021-07-21 17:14 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 22/55] rs6000: Write static initializations for overload tables Bill Schmidt
2021-07-21 17:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 23/55] rs6000: Incorporate new builtins code into the build machinery Bill Schmidt
2021-07-21 18:58 ` Segher Boessenkool
2021-07-27 3:26 ` Bill Schmidt
2021-07-27 14:23 ` Segher Boessenkool
2021-07-27 17:38 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 24/55] rs6000: Add gengtype handling to " Bill Schmidt
2021-06-17 15:19 ` [PATCH 25/55] rs6000: Add the rest of the [altivec] stanza to the builtins file Bill Schmidt
2021-06-17 15:19 ` [PATCH 26/55] rs6000: Add VSX builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 27/55] rs6000: Add available-everywhere and ancient builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 28/55] rs6000: Add power7 and power7-64 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 29/55] rs6000: Add power8-vector builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 30/55] rs6000: Add Power9 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 31/55] rs6000: Add more type nodes to support builtin processing Bill Schmidt
2021-06-17 15:19 ` [PATCH 32/55] rs6000: Add Power10 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 33/55] rs6000: Add MMA builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 34/55] rs6000: Add miscellaneous builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 35/55] rs6000: Add Cell builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 36/55] rs6000: Add remaining overloads Bill Schmidt
2021-06-17 15:19 ` [PATCH 37/55] rs6000: Execute the automatic built-in initialization code Bill Schmidt
2021-06-17 15:19 ` [PATCH 38/55] rs6000: Darwin builtin support Bill Schmidt
2021-06-17 15:19 ` [PATCH 39/55] rs6000: Add sanity to V2DI_type_node definitions Bill Schmidt
2021-06-17 15:19 ` [PATCH 40/55] rs6000: Always initialize vector_pair and vector_quad nodes Bill Schmidt
2021-06-17 15:19 ` [PATCH 41/55] rs6000: Handle overloads during program parsing Bill Schmidt
2021-06-17 15:19 ` [PATCH 42/55] rs6000: Handle gimple folding of target built-ins Bill Schmidt
2021-07-28 21:21 ` will schmidt
2021-07-29 12:42 ` Bill Schmidt
2021-08-02 13:31 ` Bill Schmidt
2021-08-02 23:43 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 43/55] rs6000: Support for vectorizing built-in functions Bill Schmidt
2021-06-17 15:19 ` [PATCH 44/55] rs6000: Builtin expansion, part 1 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-07-28 3:30 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 45/55] rs6000: Builtin expansion, part 2 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-06-17 15:19 ` [PATCH 46/55] rs6000: Builtin expansion, part 3 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-08-03 23:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 47/55] rs6000: Builtin expansion, part 4 Bill Schmidt
2021-07-27 21:06 ` will schmidt [this message]
2021-08-03 23:46 ` Segher Boessenkool
2021-08-04 0:34 ` Segher Boessenkool
2021-08-12 16:17 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 48/55] rs6000: Builtin expansion, part 5 Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-06-17 15:19 ` [PATCH 49/55] rs6000: Builtin expansion, part 6 Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-07-28 20:38 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 50/55] rs6000: Update rs6000_builtin_decl Bill Schmidt
2021-07-27 21:08 ` will schmidt
2021-08-04 0:38 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 51/55] rs6000: Miscellaneous uses of rs6000_builtin_decls_x Bill Schmidt
2021-07-27 21:08 ` will schmidt
2021-06-17 15:19 ` [PATCH 52/55] rs6000: Debug support Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-08-04 0:49 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 53/55] rs6000: Update altivec.h for automated interfaces Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-07-28 20:58 ` Bill Schmidt
2021-08-04 0:58 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 54/55] rs6000: Test case adjustments Bill Schmidt
2021-06-17 15:19 ` [PATCH 55/55] rs6000: Enable the new builtin support Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-06-25 15:25 ` [PATCHv3 00/55] Replace the Power target-specific builtin machinery Bill Schmidt
2021-07-13 13:52 ` Bill Schmidt
-- strict thread matches above, loose matches on Subject: below --
2021-06-08 18:26 [PATCHv2 " Bill Schmidt
2021-06-08 18:26 ` [PATCH 47/55] rs6000: Builtin expansion, part 4 Bill Schmidt
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