From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 4EC943983044 for ; Tue, 27 Jul 2021 21:07:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4EC943983044 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16RL4WhD069631; Tue, 27 Jul 2021 17:07:19 -0400 Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com [169.55.85.253]) by mx0a-001b2d01.pphosted.com with ESMTP id 3a2seyrp90-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 17:07:18 -0400 Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1]) by ppma01wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16RL2NFR026485; Tue, 27 Jul 2021 21:06:52 GMT Received: from b01cxnp22035.gho.pok.ibm.com (b01cxnp22035.gho.pok.ibm.com [9.57.198.25]) by ppma01wdc.us.ibm.com with ESMTP id 3a2361bdp1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 21:06:52 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16RL6qNZ37814710 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 27 Jul 2021 21:06:52 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2DB44B2065; Tue, 27 Jul 2021 21:06:52 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1AD3EB2072; Tue, 27 Jul 2021 21:06:51 +0000 (GMT) Received: from lexx (unknown [9.171.17.235]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 27 Jul 2021 21:06:50 +0000 (GMT) Message-ID: <3b98c985191f7d3d0be8ab19e6580887991c4d74.camel@vnet.ibm.com> Subject: Re: [PATCH 47/55] rs6000: Builtin expansion, part 4 From: will schmidt To: Bill Schmidt , gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org Date: Tue, 27 Jul 2021 16:06:49 -0500 In-Reply-To: <1f28ba77c244256484e000eab60d041181612ff4.1623941442.git.wschmidt@linux.ibm.com> References: <1f28ba77c244256484e000eab60d041181612ff4.1623941442.git.wschmidt@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-10.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hyWemv7CFJlXU4DhH8lWhYuxyKS7_Urb X-Proofpoint-ORIG-GUID: hyWemv7CFJlXU4DhH8lWhYuxyKS7_Urb X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-27_14:2021-07-27, 2021-07-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107270123 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jul 2021 21:07:23 -0000 On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote: > 2021-03-05 Bill Schmidt > Hi, > gcc/ > * config/rs6000/rs6000-call.c (elemrev_icode): Implement. > (ldv_expand_builtin): Likewise. > (lxvrse_expand_builtin): Likewise. > (lxvrze_expand_builtin): Likewise. > (stv_expand_builtin): Likewise. > --- > gcc/config/rs6000/rs6000-call.c | 217 ++++++++++++++++++++++++++++++++ > 1 file changed, 217 insertions(+) > > diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c > index ad3e6a4bbe5..981eabc1187 100644 > --- a/gcc/config/rs6000/rs6000-call.c > +++ b/gcc/config/rs6000/rs6000-call.c > @@ -14710,12 +14710,114 @@ new_cpu_expand_builtin (enum rs6000_gen_builtins fcode, > static insn_code > elemrev_icode (rs6000_gen_builtins fcode) > { > + switch (fcode) > + { > + default: > + gcc_unreachable (); > + case RS6000_BIF_ST_ELEMREV_V1TI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti > + : CODE_FOR_vsx_st_elemrev_v1ti); Hmm, would it be worthy to rename one of the pair so they both match "_st_" or "_store_" ? CODE_FOR_vsx_store_v1ti CODE_FOR_vsx_st_elemrev_v1ti Same for _ld_ and _load_ , but it's all a conversation for elsewhere... :-) Ok, > + case RS6000_BIF_ST_ELEMREV_V2DF: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df > + : CODE_FOR_vsx_st_elemrev_v2df); > + case RS6000_BIF_ST_ELEMREV_V2DI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di > + : CODE_FOR_vsx_st_elemrev_v2di); > + case RS6000_BIF_ST_ELEMREV_V4SF: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf > + : CODE_FOR_vsx_st_elemrev_v4sf); > + case RS6000_BIF_ST_ELEMREV_V4SI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si > + : CODE_FOR_vsx_st_elemrev_v4si); > + case RS6000_BIF_ST_ELEMREV_V8HI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi > + : CODE_FOR_vsx_st_elemrev_v8hi); > + case RS6000_BIF_ST_ELEMREV_V16QI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi > + : CODE_FOR_vsx_st_elemrev_v16qi); > + case RS6000_BIF_LD_ELEMREV_V2DF: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df > + : CODE_FOR_vsx_ld_elemrev_v2df); > + case RS6000_BIF_LD_ELEMREV_V1TI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti > + : CODE_FOR_vsx_ld_elemrev_v1ti); > + case RS6000_BIF_LD_ELEMREV_V2DI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di > + : CODE_FOR_vsx_ld_elemrev_v2di); > + case RS6000_BIF_LD_ELEMREV_V4SF: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf > + : CODE_FOR_vsx_ld_elemrev_v4sf); > + case RS6000_BIF_LD_ELEMREV_V4SI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si > + : CODE_FOR_vsx_ld_elemrev_v4si); > + case RS6000_BIF_LD_ELEMREV_V8HI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi > + : CODE_FOR_vsx_ld_elemrev_v8hi); > + case RS6000_BIF_LD_ELEMREV_V16QI: > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi > + : CODE_FOR_vsx_ld_elemrev_v16qi); > + } > + gcc_unreachable (); > return (insn_code) 0; > } ok > static rtx > ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode) > { > + rtx pat, addr; > + bool blk = (icode == CODE_FOR_altivec_lvlx > + || icode == CODE_FOR_altivec_lvlxl > + || icode == CODE_FOR_altivec_lvrx > + || icode == CODE_FOR_altivec_lvrxl); > + > + if (target == 0 > + || GET_MODE (target) != tmode > + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) No space after "!" ? (here and later on 'pat'.). > + target = gen_reg_rtx (tmode); > + > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + > + /* For LVX, express the RTL accurately by ANDing the address with -16. > + LVXL and LVE*X expand to use UNSPECs to hide their special behavior, > + so the raw address is fine. */ good comment. :-) > + if (icode == CODE_FOR_altivec_lvx_v1ti > + || icode == CODE_FOR_altivec_lvx_v2df > + || icode == CODE_FOR_altivec_lvx_v2di > + || icode == CODE_FOR_altivec_lvx_v4sf > + || icode == CODE_FOR_altivec_lvx_v4si > + || icode == CODE_FOR_altivec_lvx_v8hi > + || icode == CODE_FOR_altivec_lvx_v16qi) > + { > + rtx rawaddr; > + if (op[0] == const0_rtx) > + rawaddr = op[1]; > + else > + { > + op[0] = copy_to_mode_reg (Pmode, op[0]); > + rawaddr = gen_rtx_PLUS (Pmode, op[1], op[0]); > + } > + addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); > + addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr); > + > + emit_insn (gen_rtx_SET (target, addr)); > + } > + else > + { > + if (op[0] == const0_rtx) > + addr = gen_rtx_MEM (blk ? BLKmode : tmode, op[1]); > + else > + { > + op[0] = copy_to_mode_reg (Pmode, op[0]); > + addr = gen_rtx_MEM (blk ? BLKmode : tmode, > + gen_rtx_PLUS (Pmode, op[1], op[0])); > + } > + > + pat = GEN_FCN (icode) (target, addr); > + if (! pat) > + return 0; > + emit_insn (pat); > + } > + > return target; > } > > @@ -14723,6 +14825,42 @@ static rtx > lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op, > machine_mode tmode, machine_mode smode) > { > + rtx pat, addr; > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + > + if (op[0] == const0_rtx) > + addr = gen_rtx_MEM (tmode, op[1]); > + else > + { > + op[0] = copy_to_mode_reg (Pmode, op[0]); > + addr = gen_rtx_MEM (smode, > + gen_rtx_PLUS (Pmode, op[1], op[0])); > + } > + > + rtx discratch = gen_reg_rtx (DImode); > + rtx tiscratch = gen_reg_rtx (TImode); > + > + /* Emit the lxvr*x insn. */ > + pat = GEN_FCN (icode) (tiscratch, addr); > + if (!pat) > + return 0; > + emit_insn (pat); > + > + /* Emit a sign extension from QI,HI,WI to double (DI). */ > + rtx scratch = gen_lowpart (smode, tiscratch); > + if (icode == CODE_FOR_vsx_lxvrbx) > + emit_insn (gen_extendqidi2 (discratch, scratch)); > + else if (icode == CODE_FOR_vsx_lxvrhx) > + emit_insn (gen_extendhidi2 (discratch, scratch)); > + else if (icode == CODE_FOR_vsx_lxvrwx) > + emit_insn (gen_extendsidi2 (discratch, scratch)); > + /* Assign discratch directly if scratch is already DI. */ > + if (icode == CODE_FOR_vsx_lxvrdx) > + discratch = scratch; > + > + /* Emit the sign extension from DI (double) to TI (quad). */ > + emit_insn (gen_extendditi2 (target, discratch)); > + Ok. > > return target; > } > > @@ -14730,6 +14868,22 @@ static rtx > lxvrze_expand_builtin (rtx target, insn_code icode, rtx *op, > machine_mode tmode, machine_mode smode) > { > + rtx pat, addr; > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + > + if (op[0] == const0_rtx) > + addr = gen_rtx_MEM (tmode, op[1]); > + else > + { > + op[0] = copy_to_mode_reg (Pmode, op[0]); > + addr = gen_rtx_MEM (smode, > + gen_rtx_PLUS (Pmode, op[1], op[0])); > + } > + > + pat = GEN_FCN (icode) (target, addr); > + if (!pat) > + return 0; > + emit_insn (pat); Ok > return target; > } > > @@ -14737,6 +14891,69 @@ static rtx > stv_expand_builtin (insn_code icode, rtx *op, > machine_mode tmode, machine_mode smode) > { > + rtx pat, addr, rawaddr, truncrtx; > + op[2] = copy_to_mode_reg (Pmode, op[2]); > + > + /* For STVX, express the RTL accurately by ANDing the address with -16. > + STVXL and STVE*X expand to use UNSPECs to hide their special behavior, > + so the raw address is fine. */ > + if (icode == CODE_FOR_altivec_stvx_v2df > + || icode == CODE_FOR_altivec_stvx_v2di > + || icode == CODE_FOR_altivec_stvx_v4sf > + || icode == CODE_FOR_altivec_stvx_v4si > + || icode == CODE_FOR_altivec_stvx_v8hi > + || icode == CODE_FOR_altivec_stvx_v16qi) > + { > + if (op[1] == const0_rtx) > + rawaddr = op[2]; > + else > + { > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + rawaddr = gen_rtx_PLUS (Pmode, op[2], op[1]); > + } > + > + addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); > + addr = gen_rtx_MEM (tmode, addr); > + op[0] = copy_to_mode_reg (tmode, op[0]); > + emit_insn (gen_rtx_SET (addr, op[0])); > + } > + else if (icode == CODE_FOR_vsx_stxvrbx > + || icode == CODE_FOR_vsx_stxvrhx > + || icode == CODE_FOR_vsx_stxvrwx > + || icode == CODE_FOR_vsx_stxvrdx) > + { > + truncrtx = gen_rtx_TRUNCATE (tmode, op[0]); > + op[0] = copy_to_mode_reg (E_TImode, truncrtx); > + > + if (op[1] == const0_rtx) > + addr = gen_rtx_MEM (Pmode, op[2]); > + else > + { > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); > + } > + pat = GEN_FCN (icode) (addr, op[0]); > + if (pat) > + emit_insn (pat); > + } > + else > + { > + if (! (*insn_data[icode].operand[1].predicate) (op[0], smode)) > + op[0] = copy_to_mode_reg (smode, op[0]); > + > + if (op[1] == const0_rtx) > + addr = gen_rtx_MEM (tmode, op[2]); > + else > + { > + op[1] = copy_to_mode_reg (Pmode, op[1]); > + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); > + } > + > + pat = GEN_FCN (icode) (addr, op[0]); > + if (pat) > + emit_insn (pat); > + } > + Ok lgtm, thanks -Will > return NULL_RTX; > } >