From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id 33D243858D28 for ; Wed, 6 Sep 2023 00:17:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33D243858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-68a440a8a20so2599124b3a.3 for ; Tue, 05 Sep 2023 17:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693959455; x=1694564255; darn=gcc.gnu.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=wh96zOu9jHfC68Nk9oRNCpqZifyc73kLbqz/cCtuy98=; b=rOfsrgzEVJFEHWHCIJUACr3osCqhuRUUQ4zywZ72Dg8zJHT6K6d7Zp22NRrsMDFJj9 WvpJqKS+CP0aP+VcuPd4b8YqYBP/cVlD0QECFVsaWF1GgtZT/G/RI5hqkkMEj/0wK1V+ R7ykrloMEPnWgu5/U15+4Gdr+5pWumaUpMxPf6nZ7CdgC+1noyj/AefoLOBZrA7stvha kGqClPHk5uDrvVSUmFLboXyp/X2I7tDInSkjGvaWrXwd5v2v5uP88ECFG2t9DXQ68m2x pcZ754D3eMQQ2JV5J6rEz6rUgHPcNsGbGTpb3fVLDH3Z0kHBnIly4y2tOvz4+c//tUV+ kiHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693959455; x=1694564255; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wh96zOu9jHfC68Nk9oRNCpqZifyc73kLbqz/cCtuy98=; b=GYr0ems/+3gt/hJzJHjtuDob4mNRThikEzK9FOQVEDM7W/LxsmuunDj7dJNDnKdV6j kuxVfOk3OQY9y8S6IMAVE5n97q4ZSO5f70jnp0u+gl8wm2vHRtll16GwdP0QqCtekoM0 aC/haDjSC557sDSjMnvd6s/7/AujYmPIJ6lcm0+WXx62CxUHSoXiS7r7u6/NLz7tGB3j brDlZLtpI3XI7b1tpMAdpdZio4ZM6vx+PWOJLtt5t+Bjn49rnVvw8/lKNIRkjatWp8tw 3kthLopEDLKnJLBZSL+AAlOlU70YGqz0kqnY+xxpWNEtTDgWrfmj0EOdmV1QD/FE1jYA unow== X-Gm-Message-State: AOJu0YxllgqB0qurchhIny8dLvBVPjtJPmj1tUdBNLmoHBSP7ViVNhaP pePE9VAX+UWUPJtqJPeTNbw= X-Google-Smtp-Source: AGHT+IFER4ric5nX53NR9WPbEO8wOqnKFkZ/iULVs4tS0120jASMIQ5fM6lCCngLZa6+Gqkst+qvxg== X-Received: by 2002:a05:6a00:c96:b0:68a:6cec:e530 with SMTP id a22-20020a056a000c9600b0068a6cece530mr17587283pfv.16.1693959455007; Tue, 05 Sep 2023 17:17:35 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id e22-20020aa78256000000b0068c676f1df7sm9656490pfn.57.2023.09.05.17.17.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Sep 2023 17:17:34 -0700 (PDT) Message-ID: <3cd84da2-fe41-4a89-850c-84f3b7b26bca@gmail.com> Date: Tue, 5 Sep 2023 18:17:28 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support Content-Language: en-US To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson Cc: gcc-patches@gcc.gnu.org References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 9/5/23 06:10, Tsukasa OI wrote: > From: Tsukasa OI > > 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems > containing two instructions for conditional move and will be supported on > their Veyron V1 CPU. > > And most notably (for historical reasons), 'XVentanaCondOps' and the > standard 'Zicond' extension are functionally equivalent (only encodings and > instruction names are different). > > * czero.eqz == vt.maskc > * czero.nez == vt.maskcn > > This commit adds support for the 'XVentanaCondOps' extension by extending > 'Zicond' extension support. With this, we can now reuse the optimization > using the 'Zicond' extension for the 'XVentanaCondOps' extension. > > The specification for the 'XVentanaCondOps' extension is based on: > > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): > Parse 'XVentanaCondOps' extension. > * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New. > (TARGET_XVENTANACONDOPS): Ditto. > (TARGET_ZICOND_LIKE): New to represent targets with conditional > moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'. > * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND > with TARGET_ZICOND_LIKE. > (riscv_expand_conditional_move): Ditto. > * config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with > TARGET_ZICOND_LIKE. > * config/riscv/riscv.opt: Add new riscv_xventana_subext. > * config/riscv/zicond.md: Modify description. > (eqz_ventana): New to match corresponding czero instructions. > (nez_ventana): Ditto. > (*czero..): Emit a 'XVentanaCondOps' instruction if > 'Zicond' is not available but 'XVentanaCondOps' + RV64 is. > (*czero..): Ditto. > (*czero.eqz..opt1): Ditto. > (*czero.nez..opt2): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test, > modified from zicond-primitiveSemantics.c. > * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New > test to make sure that XVentanaCondOps instructions are disabled > on RV32. > * gcc.target/riscv/xventanacondops-xor-01.c: New test, modified > from zicond-xor-01.c. > --- > gcc/common/config/riscv/riscv-common.cc | 2 + \ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 8d8f7b4f16ed..eb10f4a3323f 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN > *total = COSTS_N_INSNS (1); > return true; > } > - else if (TARGET_ZICOND > + else if (TARGET_ZICOND_LIKE Internally we have this as: (TARGET_ZICOND || TARGET_XVENTANACONDOPS) I don't really care, so I'm happy to go with yours. > +(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")]) > +(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")]) We did these as N/n which output n or nothing: (define_code_attr n [(eq "n") (ne "")]) (define_code_attr N [(eq "") (ne "n")]) > > ;; Zicond > (define_insn "*czero.." > @@ -28,8 +31,15 @@ > (const_int 0)) > (match_operand:GPR 2 "register_operand" "r") > (const_int 0)))] > - "TARGET_ZICOND" > - "czero.\t%0,%2,%1" > + "TARGET_ZICOND_LIKE" > + { > + if (TARGET_ZICOND) > + return "czero.\t%0,%2,%1"; > + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) > + return "vt.\t%0,%2,%1"; > + else > + gcc_unreachable (); > + } > ) And so the output template ends up like this: > "* return TARGET_ZICOND ? \"czero.\t%0,%2,%1\" : \"vt.maskc\t%0,%2,%1\"; " But again, I don't care enough about this to make it a big deal and I'm happy to go with your approach. > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c > new file mode 100644 > index 000000000000..992f1425c54f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c So we're never going to have an rv32 variant. So I don't think we need rv32 xventanacondops tests. For the tests we keep, the right way to do them is with #includes. ie start with this: > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */ > +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */ Then #include the zicond variant of the test > + > +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */ > +/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */ > +/* { dg-final { scan-assembler-not "beq" } } */ > +/* { dg-final { scan-assembler-not "bne" } } */ Then you have the assembly scan strings. That way we don't duplicate the actual test code. If you could fixup the tests, then I think this will be ready to integrate. Thanks, jeff