[RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[Jeff Law]

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This is primarily Raphael's work.  All I did was adjust it to apply to 
the trunk and add the new types to generic.md's scheduling model.


The basic idea here is to make sure we have the ability to schedule the 
bitmanip instructions with a finer degree of control.  Some of the 
bitmanip instructions are likely to have differing scheduler 
characteristics across different implementations.

So rather than assign these instructions a generic "bitmanip" type, this 
patch assigns them a type based on their RTL code by using the 
<bitmanip_insn> iterator for the type.  Naturally we have to add a few 
new types.  It affects clz, ctz, cpop, min, max.

We didn't do this for things like shNadd, single bit manipulation, etc. 
We certainly could if the needs presents itself.

I threw all the new types into the generic_alu bucket in the generic 
scheduling model.  Seems as good a place as any. Someone who knows the 
sifive uarch should probably add these types (and bitmanip) to the 
sifive scheduling model.

We also noticed that the recently added orc.b didn't have a type at all. 
  So we added it as a generic bitmanip type.

This has been bootstrapped in a gcc-12 base and I've built and run the 
testsuite without regressions on the trunk.

Given it was primarily Raphael's work I could probably approve & commit 
it.  But I'd like to give the other RISC-V folks a chance to chime in.


OK for the trunk?

Jeff

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	PR target/108248
gcc/
	* config/riscv/bitmanip.md (clz, ctz, pcnt, min, max patterns): Use
	<bitmanip_insn> as the type to allow for fine grained control of
	scheduling these insns.
	* config/riscv/generic.md (generic_alu): Add bitmanip, clz, ctz, pcnt,
	min, max.
	* config/riscv/riscv.md (type attribute): Add types for clz, ctz,
	pcnt, signed and unsigned min/max.
	

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 388ef662820..44ad350c747 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -241,7 +241,7 @@
         (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
   "TARGET_ZBB"
   "<bitmanip_insn>%~\t%0,%1"
-  [(set_attr "type" "bitmanip")
+  [(set_attr "type" "<bitmanip_insn>")
    (set_attr "mode" "SI")])
 
 (define_insn "*<bitmanip_optab>disi2"
@@ -250,7 +250,7 @@
           (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
   "TARGET_64BIT && TARGET_ZBB"
   "<bitmanip_insn>w\t%0,%1"
-  [(set_attr "type" "bitmanip")
+  [(set_attr "type" "<bitmanip_insn>")
    (set_attr "mode" "SI")])
 
 (define_insn "*<bitmanip_optab>di2"
@@ -258,7 +258,7 @@
         (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
   "TARGET_64BIT && TARGET_ZBB"
   "<bitmanip_insn>\t%0,%1"
-  [(set_attr "type" "bitmanip")
+  [(set_attr "type" "<bitmanip_insn>")
    (set_attr "mode" "DI")])
 
 (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
@@ -357,7 +357,8 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 	(unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
   "TARGET_ZBB"
-  "orc.b\t%0,%1")
+  "orc.b\t%0,%1"
+  [(set_attr "type" "bitmanip")])
 
 (define_expand "bswapdi2"
   [(set (match_operand:DI 0 "register_operand")
@@ -406,7 +407,7 @@
 			   (match_operand:X 2 "reg_or_0_operand" "rJ")))]
   "TARGET_ZBB"
   "<bitmanip_insn>\t%0,%1,%z2"
-  [(set_attr "type" "bitmanip")])
+  [(set_attr "type" "<bitmanip_insn>")])
 
 ;; Optimize the common case of a SImode min/max against a constant
 ;; that is safe both for sign- and zero-extension.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b98d0ae5258..db4fabbbd92 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,7 @@
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move"))
+       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,smin,smax,umin,umax,clz,ctz,cpop"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc384d9aedf..15fbc5fe583 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -344,6 +344,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
+   min,max,minu,maxu,clz,ctz,cpop,
    atomic,condmove,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,

Re: [RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[Kito Cheng]

OK, thanks :)

On Thu, Apr 20, 2023 at 12:35 PM Jeff Law <jlaw@ventanamicro.com> wrote:
>
> This is primarily Raphael's work.  All I did was adjust it to apply to
> the trunk and add the new types to generic.md's scheduling model.
>
>
> The basic idea here is to make sure we have the ability to schedule the
> bitmanip instructions with a finer degree of control.  Some of the
> bitmanip instructions are likely to have differing scheduler
> characteristics across different implementations.
>
> So rather than assign these instructions a generic "bitmanip" type, this
> patch assigns them a type based on their RTL code by using the
> <bitmanip_insn> iterator for the type.  Naturally we have to add a few
> new types.  It affects clz, ctz, cpop, min, max.
>
> We didn't do this for things like shNadd, single bit manipulation, etc.
> We certainly could if the needs presents itself.
>
> I threw all the new types into the generic_alu bucket in the generic
> scheduling model.  Seems as good a place as any. Someone who knows the
> sifive uarch should probably add these types (and bitmanip) to the
> sifive scheduling model.
>
> We also noticed that the recently added orc.b didn't have a type at all.
>   So we added it as a generic bitmanip type.
>
> This has been bootstrapped in a gcc-12 base and I've built and run the
> testsuite without regressions on the trunk.
>
> Given it was primarily Raphael's work I could probably approve & commit
> it.  But I'd like to give the other RISC-V folks a chance to chime in.
>
>
> OK for the trunk?
>
> Jeff

Re: [RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[Andreas Schwab]

../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute `type'
make[3]: *** [Makefile:2528: s-attrtab] Error 1

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

Re: [RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[Robin Dapp]

> ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute `type'
> make[3]: *** [Makefile:2528: s-attrtab] Error 1
> 

From 582c428258ce17ffac8ef1b96b4072f3d510480f Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp@ventanamicro.com>
Date: Fri, 21 Apr 2023 09:38:06 +0200
Subject: [PATCH] riscv: Fix <bitmanip_insn> fallout.

The adjusted generic.md uses standard names instead of the types defined
in the <bitmanip_insn> iterator (that match instruction names).  Change this.

gcc/ChangeLog:

	* config/riscv/generic.md: Change standard names to insn names.
---
 gcc/config/riscv/generic.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index db4fabbbd92..2c3376628c3 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,7 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,smin,smax,umin,umax,clz,ctz,cpop"))
+       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
-- 
2.40.0

Re: [RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types

[Kito Cheng]

Hi Robin:

OK, Feel free to commit that to trunk.

and don't forgot to mention this:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109582


On Fri, Apr 21, 2023 at 3:45 PM Robin Dapp via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> > ../../gcc/config/riscv/generic.md:28:1: unknown value `smin' for attribute `type'
> > make[3]: *** [Makefile:2528: s-attrtab] Error 1
> >
>
> From 582c428258ce17ffac8ef1b96b4072f3d510480f Mon Sep 17 00:00:00 2001
> From: Robin Dapp <rdapp@ventanamicro.com>
> Date: Fri, 21 Apr 2023 09:38:06 +0200
> Subject: [PATCH] riscv: Fix <bitmanip_insn> fallout.
>
> The adjusted generic.md uses standard names instead of the types defined
> in the <bitmanip_insn> iterator (that match instruction names).  Change this.
>
> gcc/ChangeLog:
>
>         * config/riscv/generic.md: Change standard names to insn names.
> ---
>  gcc/config/riscv/generic.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
> index db4fabbbd92..2c3376628c3 100644
> --- a/gcc/config/riscv/generic.md
> +++ b/gcc/config/riscv/generic.md
> @@ -27,7 +27,7 @@ (define_cpu_unit "fdivsqrt" "pipe0")
>
>  (define_insn_reservation "generic_alu" 1
>    (and (eq_attr "tune" "generic")
> -       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,smin,smax,umin,umax,clz,ctz,cpop"))
> +       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
>    "alu")
>
>  (define_insn_reservation "generic_load" 3
> --
> 2.40.0
>
>