From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 5A8BA3857809 for ; Wed, 1 Sep 2021 06:56:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5A8BA3857809 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1816sCAB004403; Wed, 1 Sep 2021 02:56:02 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3at3uuh7c5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 01 Sep 2021 02:56:02 -0400 Received: from m0098393.ppops.net (m0098393.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 1816buvk081034; Wed, 1 Sep 2021 02:56:01 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 3at3uuh7b7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 01 Sep 2021 02:56:01 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1816qefQ018968; Wed, 1 Sep 2021 06:55:59 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma03ams.nl.ibm.com with ESMTP id 3aqcs9p46j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 01 Sep 2021 06:55:59 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1816tscD17367452 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 1 Sep 2021 06:55:54 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5433CA4073; Wed, 1 Sep 2021 06:55:54 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 72006A4062; Wed, 1 Sep 2021 06:55:52 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.34]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 1 Sep 2021 06:55:52 +0000 (GMT) To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Bill Schmidt , Michael Meissner From: "Kewen.Lin" Subject: [PATCH] rs6000: Fix some issues in rs6000_can_inline_p [PR102059] Message-ID: <3f2c6df2-e458-483c-facd-148a3cc3aead@linux.ibm.com> Date: Wed, 1 Sep 2021 14:55:51 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2A98C30C83829CC2883868C1" Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 72PSoRD7i44axSNxIkZSA__mVv8INGky X-Proofpoint-ORIG-GUID: mSNCTLGYBBufAdEGJ1l4QvVeKY4H_G3q X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-09-01_02:2021-08-31, 2021-09-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 clxscore=1015 suspectscore=0 mlxscore=0 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2109010035 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Sep 2021 06:56:14 -0000 This is a multi-part message in MIME format. --------------2A98C30C83829CC2883868C1 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 7bit Hi! This patch is to fix the inconsistent behaviors for non-LTO mode and LTO mode. As Martin pointed out, currently the function rs6000_can_inline_p simply makes it inlinable if callee_tree is NULL, but it's wrong, we should use the command line options from target_option_default_node as default. It also replaces rs6000_isa_flags with the one from target_option_default_node when caller_tree is NULL as rs6000_isa_flags could probably change since initialization. It also extends the scope of the check for the case that callee has explicit set options, for test case pr102059-2.c inlining can happen unexpectedly before, it's fixed accordingly. As Richi/Mike pointed out, some tuning flags like MASK_P8_FUSION can be neglected for inlining, this patch also exludes them when the callee is attributed by always_inline. Bootstrapped and regtested on powerpc64le-linux-gnu Power9. BR, Kewen ----- gcc/ChangeLog: PR ipa/102059 * config/rs6000/rs6000.c (rs6000_can_inline_p): Adjust with target_option_default_node and consider always_inline_safe flags. gcc/testsuite/ChangeLog: PR ipa/102059 * gcc.target/powerpc/pr102059-1.c: New test. * gcc.target/powerpc/pr102059-2.c: New test. * gcc.target/powerpc/pr102059-3.c: New test. * gcc.target/powerpc/pr102059-4.c: New test. --------------2A98C30C83829CC2883868C1 Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="0001-rs6000-Fix-some-issues-in-rs6000_can_inline_p-PR1020.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-rs6000-Fix-some-issues-in-rs6000_can_inline_p-PR1020.pa"; filename*1="tch" --- gcc/config/rs6000/rs6000.c | 87 +++++++++++------ gcc/testsuite/gcc.target/powerpc/pr102059-1.c | 24 +++++ gcc/testsuite/gcc.target/powerpc/pr102059-2.c | 20 ++++ gcc/testsuite/gcc.target/powerpc/pr102059-3.c | 95 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 22 +++++ 5 files changed, 221 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr102059-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr102059-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr102059-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr102059-4.c diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 46b8909104e..c2582a3efab 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -25058,45 +25058,78 @@ rs6000_generate_version_dispatcher_body (void *node_p) static bool rs6000_can_inline_p (tree caller, tree callee) { - bool ret = false; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller); tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee); - /* If the callee has no option attributes, then it is ok to inline. */ + /* If the caller/callee has option attributes, then use them. + Otherwise, use the command line options. */ if (!callee_tree) - ret = true; + callee_tree = target_option_default_node; + if (!caller_tree) + caller_tree = target_option_default_node; + + struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); + struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); + HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags; + HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; + + bool always_inline = + (DECL_DISREGARD_INLINE_LIMITS (callee) + && lookup_attribute ("always_inline", DECL_ATTRIBUTES (callee))); + + /* Some flags such as fusion can be tolerated for always inlines. */ + unsigned HOST_WIDE_INT always_inline_safe_mask = + (MASK_P8_FUSION | MASK_P10_FUSION | OPTION_MASK_SAVE_TOC_INDIRECT + | OPTION_MASK_P8_FUSION_SIGN | OPTION_MASK_P10_FUSION_LD_CMPI + | OPTION_MASK_P10_FUSION_2LOGICAL | OPTION_MASK_P10_FUSION_LOGADD + | OPTION_MASK_P10_FUSION_ADDLOG | OPTION_MASK_P10_FUSION_2ADD + | OPTION_MASK_PCREL_OPT); + + if (always_inline) { + caller_isa &= ~always_inline_safe_mask; + callee_isa &= ~always_inline_safe_mask; + } - else + /* The callee's options must be a subset of the caller's options, i.e. + a vsx function may inline an altivec function, but a no-vsx function + must not inline a vsx function. */ + if ((caller_isa & callee_isa) != callee_isa) { - HOST_WIDE_INT caller_isa; - struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); - HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags; - HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; - - /* If the caller has option attributes, then use them. - Otherwise, use the command line options. */ - if (caller_tree) - caller_isa = TREE_TARGET_OPTION (caller_tree)->x_rs6000_isa_flags; - else - caller_isa = rs6000_isa_flags; + if (TARGET_DEBUG_TARGET) + fprintf (stderr, + "rs6000_can_inline_p:, caller %s, callee %s, cannot " + "inline since callee's options set isn't a subset of " + "caller's options set.\n", + get_decl_name (caller), get_decl_name (callee)); + return false; + } - /* The callee's options must be a subset of the caller's options, i.e. - a vsx function may inline an altivec function, but a no-vsx function - must not inline a vsx function. However, for those options that the - callee has explicitly enabled or disabled, then we must enforce that - the callee's and caller's options match exactly; see PR70010. */ - if (((caller_isa & callee_isa) == callee_isa) - && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)) - ret = true; + /* For those options that the callee has explicitly enabled or disabled, + then we must enforce that the callee's and caller's options match + exactly; see PR70010. */ + HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit; + if (always_inline) + explicit_isa &= ~always_inline_safe_mask; + if ((caller_isa & explicit_isa) != (callee_isa & explicit_isa)) + { + if (TARGET_DEBUG_TARGET) + fprintf (stderr, + "rs6000_can_inline_p:, caller %s, callee %s, cannot " + "inline since callee's options set isn't a subset of " + "caller's options set by considering callee's " + "explicitly set options.\n", + get_decl_name (caller), get_decl_name (callee)); + return false; } if (TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n", - get_decl_name (caller), get_decl_name (callee), - (ret ? "can" : "cannot")); + fprintf (stderr, + "rs6000_can_inline_p:, caller %s, callee %s, can inline.\n", + get_decl_name (caller), get_decl_name (callee)); - return ret; + return true; } + /* Allocate a stack temp and fixup the address so it meets the particular memory requirements (either offetable or REG+REG addressing). */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-1.c b/gcc/testsuite/gcc.target/powerpc/pr102059-1.c new file mode 100644 index 00000000000..d2a002cf141 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr102059-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_htm_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ + +/* Verify it emits inlining error msg at non-LTO mode. */ + +#include + +static inline int __attribute__ ((always_inline)) +foo (int *b) /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + int res = _HTM_STATE(__builtin_ttest()); + *b += res; + return *b; +} + +#pragma GCC target "cpu=power10" +int +bar (int *a) +{ + *a = foo (a); /* { dg-message "called from here" } */ + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-2.c b/gcc/testsuite/gcc.target/powerpc/pr102059-2.c new file mode 100644 index 00000000000..1d5d6c38bf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr102059-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-vsx" } */ + +/* Verify it emits inlining error msg when the callee has explicit + disabling option from command line. */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__)) +foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + c = a + b; +} + +__attribute__ ((target ("vsx"))) +int main () +{ + foo (); /* { dg-message "called from here" } */ + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-3.c b/gcc/testsuite/gcc.target/powerpc/pr102059-3.c new file mode 100644 index 00000000000..9684cab986a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr102059-3.c @@ -0,0 +1,95 @@ +/* { dg-do compile } */ +/* -Wno-attributes suppresses always_inline warnings. */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -Wno-attributes" } */ + +/* Verify it doesn't emit inlining error msg since some mismatched + features are considered as safe for always_inline. */ + +/* 1. Callee enables Power8 fusion implicitly, while caller + with Power9 doesn't support power8 fusion at all. */ + +__attribute__ ((always_inline)) +int callee1 (int *b) +{ + *b += 1; + return *b; +} + +#pragma GCC target "cpu=power9" +int caller1 (int *a) +{ + *a = callee1 (a); + return 0; +} + +/* 2. Caller enables indirect toc save feature while callee + disables it explicitly. */ + +#pragma GCC target "save-toc-indirect" +__attribute__ ((always_inline)) +int callee2 (int *b) +{ + *b += 2; + return *b; +} + +#pragma GCC target "no-save-toc-indirect" +int caller2 (int *a) +{ + *a = callee2 (a); + return 0; +} + +/* 3. Caller disables Power10 fusion explicitly, while callee + still supports it as Power10 turns it on by default. */ + +#pragma GCC target "cpu=power10" +__attribute__ ((always_inline)) +int callee3 (int *b) +{ + *b += 3; + return *b; +} + +#pragma GCC target "cpu=power10,no-power10-fusion" +int caller3 (int *a) +{ + *a = callee3 (a); + return 0; +} + +/* 4. Caller enables Power10 fusion implicitly, while callee + disables it explicitly. */ + +#pragma GCC target "no-power10-fusion" +__attribute__ ((always_inline)) +int callee4 (int *b) +{ + *b += 4; + return *b; +} + +#pragma GCC target "cpu=power10" +int caller4 (int *a) +{ + *a = callee4 (a); + return 0; +} + +/* 5. Caller disables pcrel-opt while callee enables it explicitly. */ + +#pragma GCC target "cpu=power10,no-pcrel-opt" +__attribute__ ((always_inline)) +int callee5 (int *b) +{ + *b += 5; + return *b; +} + +#pragma GCC target "cpu=power10,pcrel-opt" +int caller5 (int *a) +{ + *a = callee5 (a); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c new file mode 100644 index 00000000000..0f27f2ce7d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* -Wno-attributes suppresses always_inline warnings. */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-power8-fusion -Wno-attributes" } */ + +/* Verify it doesn't emit inlining error msg since the flag power8 + fusion is considered as safe for always_inline, it's still safe + even the flag is set explicitly. */ + +__attribute__ ((always_inline)) +int foo (int *b) +{ + *b += 10; + return *b; +} + +#pragma GCC target "power8-fusion" +int bar (int *a) +{ + *a = foo (a); + return 0; +} + -- 2.17.1 --------------2A98C30C83829CC2883868C1--