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From: Robin Dapp <rdapp.gcc@gmail.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: rdapp.gcc@gmail.com, gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] internal-fn: Do not force vcond operand to reg.
Date: Mon, 13 May 2024 08:18:31 +0200	[thread overview]
Message-ID: <3ff9db2b-012f-4311-afa7-314d0b50f976@gmail.com> (raw)
In-Reply-To: <CAFiYyc3iX50j87=u9TBr7jVf6mi+hZ0P4vQZP61C_exG8nQFoA@mail.gmail.com>

> How does this make a difference in the end?  I'd expect say forwprop to
> fix things?

In general we try to only add the masking "boilerplate" of our
instructions at split time so fwprop, combine et al. can do their
work uninhibited of it (and we don't need numerous
(if_then_else ... (if_then_else) ...) combinations in our patterns).
A vec constant we expand directly to a masked representation, though
which makes further simplification difficult.  I can experiment with
changing that if preferred.

My thinking was, however, that for other operations like binops we
directly emit the right variant via expand_operands without
forcing to a reg and don't even need to fwprop so I wanted to
imitate that.

Regards
 Robin


  reply	other threads:[~2024-05-13  6:18 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-10 13:17 Robin Dapp
2024-05-10 13:21 ` Richard Biener
2024-05-13  6:18   ` Robin Dapp [this message]
2024-05-13  7:53     ` Richard Biener
2024-05-13 14:14       ` Robin Dapp
2024-05-13 14:19         ` Richard Biener
2024-05-17 10:35           ` Robin Dapp

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