From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.37]) by sourceware.org (Postfix) with UTF8SMTPS id 0AA0D3858CDA for ; Fri, 12 May 2023 06:19:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0AA0D3858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683872337; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=Xif8D3BYSSfJ8Oy2mOF14/Lucix+YHJq0D91HYHvNMI=; b=lJI+ckdMEWJqoPDXgiGq0E/VfRP6INzIAYJ/24mgQgDF2bAlFhVCTRDWwl4q+oHQSCQqS/ RxIqpRS+b5YttdHX8USQ7t+LH3ylOEXRez80rDDgUGJWOBcXl5vb2wdT8y2l5I/T7i9tjG NJpVpIWCIQ2MCpR7Yxs2fsXGVkLsNwqld2neW2Qm5Tk+OMLAquG0oba9Tj2U4MF0Ib7+On 4IvREUW2OT5PFakhu/0QTSKQFMKKMq6d3tAcmAfvb2gY8BYU1dsdWlJFKWIzDyaTNibrK2 ydq6ydKBTayhFPAeCvEnOFBEtKmdpkGA6jIl1P8UAN1G8uu6VIAE1nsB86tDKw== Message-Id: <4002df66326dc8be0fcd50c4daca77e599bd422a.1683871682.git.jie.mei@oss.cipunited.com> Date: Fri, 12 May 2023 14:18:56 +0800 In-Reply-To: X-Lms-Return-Path: Subject: [PATCH v2 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 Mime-Version: 1.0 References: Content-Transfer-Encoding: 8bit To: From: "Jie Mei" X-Mailer: git-send-email 2.40.1 Content-Type: multipart/alternative; boundary=1e740f861cb7bc2fa7ac4631087eba6416b81b503afb22de8b7d3387712b X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --1e740f861cb7bc2fa7ac4631087eba6416b81b503afb22de8b7d3387712b Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (ISA_HAS_LL_SC): Same as above. --- gcc/config/mips/mips.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a5c121088b7..1947be25aca 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1247,7 +1247,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) =20 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ -#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >=3D 6) +#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >=3D 6 \ + || ISA_HAS_MIPS16E2) =20 /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. @@ -1340,7 +1341,8 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >=3D 2 && !TARGET_MIPS16) =20 /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >=3D MIPS_ISA_MIPS2 || TARGET_MIPS3900) &&= !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >=3D MIPS_ISA_MIPS2 || TARGET_MIPS3900) \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1349,7 +1351,8 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >=3D MIPS_ISA_MIPS2 && !TARGET_MIPS5900 &&= !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >=3D MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ --=20 2.40.1= --1e740f861cb7bc2fa7ac4631087eba6416b81b503afb22de8b7d3387712b--