Re: [PATCH V2] RISC-V: Fix error combine of pred_mov pattern

[Jeff Law <jeffreyalaw@gmail.com>]

On 8/10/23 06:21, Lehua Ding wrote:

> +;; vle.v/vse.v,vmv.v.v
> +(define_insn_and_split "*pred_mov<mode>"
> +  [(set (match_operand:V_VLS 0 "nonimmediate_operand"            "=vr,    vr,    vd,     m,    vr,    vr")
> +    (if_then_else:V_VLS
> +      (unspec:<VM>
> +        [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,   Wc1,    vm, vmWc1,   Wc1,   Wc1")
> +         (match_operand 4 "vector_length_operand"              "   rK,    rK,    rK,    rK,    rK,    rK")
> +         (match_operand 5 "const_int_operand"                  "    i,     i,     i,     i,     i,     i")
> +         (match_operand 6 "const_int_operand"                  "    i,     i,     i,     i,     i,     i")
> +         (match_operand 7 "const_int_operand"                  "    i,     i,     i,     i,     i,     i")
> +         (reg:SI VL_REGNUM)
> +         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> +      (match_operand:V_VLS 3 "reg_or_mem_operand"              "    m,     m,     m,    vr,    vr,    vr")
> +      (match_operand:V_VLS 2 "vector_merge_operand"            "    0,    vu,    vu,    vu,    vu,     0")))]
> +  "TARGET_VECTOR && (register_operand (operands[0], <MODE>mode)
> +                     || register_operand (operands[3], <MODE>mode))"
Just a formatting nit in the pattern's condition.

"(TARGET_VECTOR
   && (register_operand (operands[0], <MODE>mode)
       || register_operand (operands[3], <MODE>mode)))"

OK with that change.  No need to wait for another approval.  Just update 
the patch, commit and post the committed patch to the list for archival 
purposes.

Thanks, and sorry for the long wait.  I just get busy sometimes.

jeff