[PATCH] avoid xmm register in SSE float->int conversions

[Uros Bizjak <uros@kss-loka.si>]

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Hello!

For the DF->SI testcases like this:

int test1(double a) {
        return sin(a);
}

current mainline gcc produces following code for -march=pentium4:
        ...
        fsin
        fstpl   (%esp)
        movsd   (%esp), %xmm0
        cvttsd2si       %xmm0, %eax
        ...
        ret

At least for pentium4 (and perhaps other !TARGET_K8 targets), xmm 
register could be avoided, as cvttsd2si can convert directly from memory 
to integer register. Attached patch introduces a couple of peephole2 
optimizers to get rid of extra movsd.
Unfortunatelly, combine pass can't be used in this case, because all 
necessary moves are generated in greg pass _after_ combine.

With attached patch, gcc generates following code:
test1:
        subl    $12, %esp
        fldl    16(%esp)
        fsin
        fstpl   (%esp)
        cvttsd2si       (%esp), %eax
        addl    $12, %esp
        ret

BTW: A small bug was fixed: *fix_trunchi_1 should have its split 
constraint defined.

Bootstrapped on i686-pc-linux-gnu, regtest in progres, c and c++.

2004-10-18  Uros Bizjak  <uros@kss-loka.si>

    * config/i386/i386.md (fix_truncsfdi_sse, fix_truncdfdi_sse,
    fix_truncsfsi_sse, fix_truncdfsi_sse): Add peephole2
    optimizers to avoid mem->sse_reg->reg in FP->int
    conversions for !TARGET_K8.
    (*fix_trunchi_1): Add "&& 1" as split constraint.

Uros.

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Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.562
diff -u -r1.562 i386.md
--- i386.md	18 Oct 2004 13:01:31 -0000	1.562
+++ i386.md	18 Oct 2004 13:36:27 -0000
@@ -4181,6 +4181,15 @@
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "double,vector")])
 
+(define_peephole2
+  [(set (match_operand:SF 0 "register_operand" "")
+	(match_operand:SF 1 "memory_operand" ""))
+   (set (match_operand:DI 2 "register_operand" "")
+	(fix:DI (match_dup 0)))]
+  "!TARGET_K8"
+  [(set (match_dup 2) (fix:DI (match_dup 1)))]
+  "")
+
 ;; Avoid vector decoded form of the instruction.
 (define_peephole2
   [(match_scratch:SF 2 "x")
@@ -4200,6 +4209,15 @@
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,vector")])
 
+(define_peephole2
+  [(set (match_operand:DF 0 "register_operand" "")
+	(match_operand:DF 1 "memory_operand" ""))
+   (set (match_operand:DI 2 "register_operand" "")
+	(fix:DI (match_dup 0)))]
+  "!TARGET_K8"
+  [(set (match_dup 2) (fix:DI (match_dup 1)))]
+  "")
+
 ;; Avoid vector decoded form of the instruction.
 (define_peephole2
   [(match_scratch:DF 2 "Y")
@@ -4318,6 +4336,15 @@
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,vector")])
 
+(define_peephole2
+  [(set (match_operand:SF 0 "register_operand" "")
+	(match_operand:SF 1 "memory_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+	(fix:SI (match_dup 0)))]
+  "!TARGET_K8"
+  [(set (match_dup 2) (fix:SI (match_dup 1)))]
+  "")
+
 ;; Avoid vector decoded form of the instruction.
 (define_peephole2
   [(match_scratch:SF 2 "x")
@@ -4337,6 +4364,15 @@
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,vector")])
 
+(define_peephole2
+  [(set (match_operand:DF 0 "register_operand" "")
+	(match_operand:DF 1 "memory_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+	(fix:SI (match_dup 0)))]
+  "!TARGET_K8"
+  [(set (match_dup 2) (fix:SI (match_dup 1)))]
+  "")
+
 ;; Avoid vector decoded form of the instruction.
 (define_peephole2
   [(match_scratch:DF 2 "Y")
@@ -4405,7 +4441,7 @@
    && !reload_completed && !reload_in_progress
    && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
   "#"
-  ""
+  "&& 1"
   [(const_int 0)]
 {
   ix86_optimize_mode_switching = 1;