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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id p21-20020aa78615000000b005a8c16fcb78sm4839919pfn.56.2023.03.05.10.13.46 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Mar 2023 10:13:46 -0800 (PST) Message-ID: <41ba8a45-b4a6-aaf4-1b7a-6e7a7d2dec4f@gmail.com> Date: Sun, 5 Mar 2023 11:13:45 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] Content-Language: en-US To: gcc-patches@gcc.gnu.org References: <20221209182510.43515-1-rzinsly@ventanamicro.com> From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2/23/23 14:23, Andrew Pinski via Gcc-patches wrote: > On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly > wrote: >> >> Changes since v1: >> - Fixed formatting issues. >> - Added a name to the define_insn_and_split pattern. >> - Set the target on the 'dg-do compile' in pr106602.c. >> - Removed the rv32 restriction in pr95632.c. >> >> -- >8 -- >> >> Due to RISC-V limitations on operations with big constants combine >> is failing to match such operations and is not being able to >> produce optimal code as it keeps splitting them. By pretending we >> can do those operations we can get more opportunities for >> simplification of surrounding instructions. >> >> 2022-12-06 Raphael Moreira Zinsly >> Jeff Law >> >> gcc/Changelog: >> PR target/95632 >> PR target/106602 >> * config/riscv/riscv.md: New pattern to simulate complex >> const_int loads. >> >> gcc/testsuite/ChangeLog: >> * gcc.target/riscv/pr95632.c: New test. >> * gcc.target/riscv/pr106602.c: New test. >> --- >> gcc/config/riscv/riscv.md | 15 +++++++++++++++ >> gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++ >> gcc/testsuite/gcc.target/riscv/pr95632.c | 15 +++++++++++++++ >> 3 files changed, 44 insertions(+) >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c >> >> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >> index df57e2b0b4a..b0daa4b19eb 100644 >> --- a/gcc/config/riscv/riscv.md >> +++ b/gcc/config/riscv/riscv.md >> @@ -1667,6 +1667,21 @@ >> MAX_MACHINE_MODE, &operands[3], TRUE); >> }) >> >> +;; Pretend to have the ability to load complex const_int in order to get >> +;; better code generation around them. >> +(define_insn_and_split "*mvconst_internal" >> + [(set (match_operand:GPR 0 "register_operand" "=r") >> + (match_operand:GPR 1 "splittable_const_int_operand" "i"))] >> + "cse_not_expected" > > This is just way broken. This should be combined with the normal move > instructions and just be a define_split. > See PR 108892 for a testcase which shows this breaking how the > register allocator thinks it should work. I'm pretty sure that won't work. You need them exposed as a define_insn so that they can act as a bridge pattern for combine. You don't want to expose before combine as that'll regress things in a variety of other ways. You don't want the bridge form to survive after splitting. Hence define_insn_and_split. I haven't looked at that bug in detail, but Raphael and I certainly will. jeff