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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id 13-20020a92c64d000000b00300f4e0d41bsm729681ill.57.2022.11.17.15.12.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Nov 2022 15:12:41 -0800 (PST) Message-ID: <42256d39-d815-50b9-61f8-4c07429e0c55@gmail.com> Date: Thu, 17 Nov 2022 16:12:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc Content-Language: en-US To: Philipp Tomsich , gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> <20221112212943.3068249-4-philipp.tomsich@vrull.eu> From: Jeff Law In-Reply-To: <20221112212943.3068249-4-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/12/22 14:29, Philipp Tomsich wrote: > When if-conversion in noce_try_store_flag_mask starts the sequence off > with an order-operator, our patterns for vt.maskc will receive the > result of the order-operator as a register argument; consequently, > they can't know that the result will be either 1 or 0. > > To convey this information (and make vt.maskc applicable), we wrap > the result of the order-operator in a eq/ne against (const_int 0). > This commit adds the split pattern to handle these cases. > > gcc/ChangeLog: > > * config/riscv/xventanacondops.md: Add split to wrap an an > order-operator suitably for generating vt.maskc. > > Signed-off-by: Philipp Tomsich > > Ref vrull/gcc#157 > > RISC-V: Recognize 'ge'/'le' operators as 'slt'/'sgt' > > During if-conversion, if noce_try_store_flag_mask succeeds, we may see > if (cur < next) { > next = 0; > } > transformed into > 27: r82:SI=ltu(r76:DI,r75:DI) > REG_DEAD r76:DI > 28: r81:SI=r82:SI^0x1 > REG_DEAD r82:SI > 29: r80:DI=zero_extend(r81:SI) > REG_DEAD r81:SI > > This currently escapes the combiner, as RISC-V does not have a pattern > to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in > this commit, we match such cases. > > gcc/ChangeLog: > > * config/riscv/predicates.md (anyge_operator): Define. > (anygt_operator): Define. > (anyle_operator): Define. > (anylt_operator): Define. > * config/riscv/riscv.md (*sge_): Add a > pattern to map 'geu' onto slt w/ reversed operands. > * config/riscv/riscv.md: Helpers for ge & le. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xventanacondops-le-01.c: New test. > * gcc.target/riscv/xventanacondops-lt-03.c: New test. Presumably the two splitters in riscv.md can't live in xventanacondops.md due to ordering issues? OK once we've cleared the non-technical hurdles to committing vendor specific extensions. Jeff