From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id CD837397EC14 for ; Tue, 27 Jul 2021 21:07:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD837397EC14 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16RL3hMn066409; Tue, 27 Jul 2021 17:07:06 -0400 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 3a2qpd40t3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 17:07:05 -0400 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16RL2D5L002697; Tue, 27 Jul 2021 21:07:04 GMT Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by ppma04wdc.us.ibm.com with ESMTP id 3a235n3gr7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 21:07:04 +0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16RL73d745089262 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 27 Jul 2021 21:07:03 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 65FC111206F; Tue, 27 Jul 2021 21:07:03 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C66D112072; Tue, 27 Jul 2021 21:07:02 +0000 (GMT) Received: from lexx (unknown [9.171.17.235]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 27 Jul 2021 21:07:02 +0000 (GMT) Message-ID: <4285eb69fc2c51e7c2235facda1b9400cb7e806c.camel@vnet.ibm.com> Subject: Re: [PATCH 48/55] rs6000: Builtin expansion, part 5 From: will schmidt To: Bill Schmidt , gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org Date: Tue, 27 Jul 2021 16:07:00 -0500 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-10.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: QhB-tuO6rBEHE4c8C1OnlwS0UJFyYS8u X-Proofpoint-GUID: QhB-tuO6rBEHE4c8C1OnlwS0UJFyYS8u X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-27_14:2021-07-27, 2021-07-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107270123 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jul 2021 21:07:08 -0000 On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote: > 2021-06-17 Bill Schmidt > Hi, > gcc/ > * config/rs6000/rs6000-call.c (new_mma_expand_builtin): > Implement. Ok, > --- > gcc/config/rs6000/rs6000-call.c | 103 ++++++++++++++++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c > index 981eabc1187..e1b685fb874 100644 > --- a/gcc/config/rs6000/rs6000-call.c > +++ b/gcc/config/rs6000/rs6000-call.c > @@ -14962,6 +14962,109 @@ static rtx > new_mma_expand_builtin (tree exp, rtx target, insn_code icode, > rs6000_gen_builtins fcode) > { > + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); > + tree arg; > + call_expr_arg_iterator iter; > + const struct insn_operand_data *insn_op; > + rtx op[MAX_MMA_OPERANDS]; > + unsigned nopnds = 0; > + bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; > + machine_mode tmode = VOIDmode; > + > + if (!void_func) > + { > + tmode = insn_data[icode].operand[0].mode; > + if (!target > + || GET_MODE (target) != tmode > + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) > + target = gen_reg_rtx (tmode); > + op[nopnds++] = target; > + } > + else > + target = const0_rtx; > + > + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) > + { > + if (arg == error_mark_node) > + return const0_rtx; > + > + rtx opnd; > + insn_op = &insn_data[icode].operand[nopnds]; > + if (TREE_CODE (arg) == ADDR_EXPR > + && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0)))) > + opnd = DECL_RTL (TREE_OPERAND (arg, 0)); > + else > + opnd = expand_normal (arg); > + > + if (!(*insn_op->predicate) (opnd, insn_op->mode)) > + { > + if (!strcmp (insn_op->constraint, "n")) > + { > + if (!CONST_INT_P (opnd)) > + error ("argument %d must be an unsigned literal", nopnds); > + else > + error ("argument %d is an unsigned literal that is " > + "out of range", nopnds); > + return const0_rtx; > + } > + opnd = copy_to_mode_reg (insn_op->mode, opnd); > + } > + > + /* Some MMA instructions have INOUT accumulator operands, so force > + their target register to be the same as their input register. */ > + if (!void_func > + && nopnds == 1 > + && !strcmp (insn_op->constraint, "0") > + && insn_op->mode == tmode > + && REG_P (opnd) > + && (*insn_data[icode].operand[0].predicate) (opnd, tmode)) > + target = op[0] = opnd; > + > + op[nopnds++] = opnd; > + } > + > + rtx pat; > + switch (nopnds) > + { > + case 1: > + pat = GEN_FCN (icode) (op[0]); > + break; > + case 2: > + pat = GEN_FCN (icode) (op[0], op[1]); > + break; > + case 3: > + /* The ASSEMBLE builtin source operands are reversed in little-endian > + mode, so reorder them. */ > + if (fcode == RS6000_BIF_ASSEMBLE_PAIR_V_INTERNAL && !WORDS_BIG_ENDIAN) > + std::swap (op[1], op[2]); > + pat = GEN_FCN (icode) (op[0], op[1], op[2]); > + break; > + case 4: > + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); > + break; > + case 5: > + /* The ASSEMBLE builtin source operands are reversed in little-endian > + mode, so reorder them. */ I'd be tempted to consolidate the source operand reversal comments for RS6000_BIF_ASSEMBLE_PAIR_V_INTERNAL and RS6000_BIF_ASSEMBLE_ACC_INTERNAL.. up at the start of the case statement.. but actually i think this makes sense as-is. Ok. > + if (fcode == RS6000_BIF_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN) > + { > + std::swap (op[1], op[4]); > + std::swap (op[2], op[3]); > + } > + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); > + break; > + case 6: > + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); > + break; > + case 7: > + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]); > + break; > + default: > + gcc_unreachable (); > + } > + if (!pat) > + return NULL_RTX; > + emit_insn (pat); > + Ok, lgtm, thanks -Will > return target; > } >