From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 3FA643858D35 for ; Fri, 16 Jun 2023 13:32:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3FA643858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-97881a996a0so105948066b.0 for ; Fri, 16 Jun 2023 06:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686922331; x=1689514331; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:cc:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=rUYC2HkdRcJkJCFb7NghkF5RwsA2xq94YqUQs1SCwlU=; b=ixafV/TLhOoGsWJqUTOMiUGK88gDA/pkdugp6lfwCVQso1Bk67Ue/ZhwhTozo13dAi ao0TxkaMhALrqFZOKra6mkx7VU+f9lxk9JnB1byQZ/7DET4dYpn2Eo9Vn8wzNLerbjr6 BJPHNt5p2fXciVfcPI4jYvwo/1LI8rH5mk6MlBGo66NN6e7YFkUvEX3lfRs7eGXJUzKF /5z9A/kZieUAdCYfOg3l3MEhj/VUA0Nx5Nv+tZaCdIuWFjjXTHi25LjXJP81V2/OpZiX YBJO8w5uGAMHgBJeFqtRkvNIlVNafHoSmeN7jCwF6ldFyRVx6D7xD/ugOlSs6aI+qnTa sCGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686922331; x=1689514331; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:cc:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rUYC2HkdRcJkJCFb7NghkF5RwsA2xq94YqUQs1SCwlU=; b=c6hnZSi+PomJ7poEIo9qMjK7M2xtj4S+w9ERXO9ZExXx6yeH3veIkfnfwocFBOzYMO kpsTTJnOdkTABiCe4AjLbz6wL/qs7y1WwvlPzz0XsH+hRzAoMq3suw8w8H/d304E/bud BpIkweg3BrX69J+J4SSQAP9T9ojvFvU8R9V59yUb13+yz7EEfe5k0d44UaN1fPsh1NVE 3wxdMQ3uZKYnuSi4jtrHG8CimKi1ToBuW8BeTqKbQRHbMUuc4jeivm38F+RSPlEhPesl qqwLhOT23aGozFj8hcH8r5SUXQntwKCLBJXXvaD9BhgsuZjmutd8Qx/Jbhc4LOby3WkC lozQ== X-Gm-Message-State: AC+VfDxcSGgxoW7kPrJxqnRUGILwO54dPFjNr2uHuoSDte1DGcOjo8WC UBIl3rz5eSSSi1qgGoev/cHlzsJ2t6g= X-Google-Smtp-Source: ACHHUZ6UsGnR8KOVYVedIpl0PI9+/CnW+A/HamAIK8pSTSbuKPeFMwSR84nK3rhtz3YJagiv5Y5syw== X-Received: by 2002:a17:907:a41e:b0:978:8ecd:fa75 with SMTP id sg30-20020a170907a41e00b009788ecdfa75mr2032770ejc.9.1686922331064; Fri, 16 Jun 2023 06:32:11 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id s20-20020a170906961400b009829d2e892csm2446287ejx.15.2023.06.16.06.32.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jun 2023 06:32:10 -0700 (PDT) Message-ID: <4288ccbd-68dd-a58d-c068-e352111f21bc@gmail.com> Date: Fri, 16 Jun 2023 15:32:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Subject: [PATCH v3] RISC-V: Add autovec FP unary operations. Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , jeffreyalaw References: <490fd4af-75d2-de76-fa74-f9ebb478b8b8@gmail.com> <64cd759b-d2c2-121d-b960-4a806b8da27a@gmail.com> From: Robin Dapp In-Reply-To: <64cd759b-d2c2-121d-b960-4a806b8da27a@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, changes from V2: - No longer dependent on testsuite changes. - Add zvfhmin-1.c unary test cases. Regards Robin This patch adds floating-point autovec expanders for vfneg, vfabs as well as vfsqrt and the accompanying tests. Similary to the binop tests, there are flavors for zvfh now. gcc/ChangeLog: * config/riscv/autovec.md (2): Add unop expanders. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP. * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Add unops. --- gcc/config/riscv/autovec.md | 36 ++++++++++++++- .../riscv/rvv/autovec/unop/abs-run.c | 46 ++++++++++--------- .../riscv/rvv/autovec/unop/abs-rv32gcv.c | 3 +- .../riscv/rvv/autovec/unop/abs-rv64gcv.c | 3 +- .../riscv/rvv/autovec/unop/abs-template.h | 17 +++++-- .../riscv/rvv/autovec/unop/abs-zvfh-run.c | 35 ++++++++++++++ .../riscv/rvv/autovec/unop/vfsqrt-run.c | 30 ++++++++++++ .../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 12 +++++ .../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 12 +++++ .../riscv/rvv/autovec/unop/vfsqrt-template.h | 31 +++++++++++++ .../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 33 +++++++++++++ .../riscv/rvv/autovec/unop/vneg-run.c | 8 ++-- .../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 3 +- .../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 3 +- .../riscv/rvv/autovec/unop/vneg-template.h | 5 +- .../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 26 +++++++++++ .../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 16 ++++++- 17 files changed, 284 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 94452c932a4..5b84eaaf052 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -513,7 +513,7 @@ (define_expand "2" }) ;; ------------------------------------------------------------------------------- -;; - ABS expansion to vmslt and vneg +;; - [INT] ABS expansion to vmslt and vneg. ;; ------------------------------------------------------------------------------- (define_expand "abs2" @@ -532,6 +532,40 @@ (define_expand "abs2" DONE; }) +;; ------------------------------------------------------------------------------- +;; ---- [FP] Unary operations +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfneg.v/vfabs.v +;; ------------------------------------------------------------------------------- +(define_expand "2" + [(set (match_operand:VF_AUTO 0 "register_operand") + (any_float_unop_nofrm:VF_AUTO + (match_operand:VF_AUTO 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + +;; ------------------------------------------------------------------------------- +;; - [FP] Square root +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfsqrt.v +;; ------------------------------------------------------------------------------- +(define_expand "2" + [(set (match_operand:VF_AUTO 0 "register_operand") + (any_float_unop:VF_AUTO + (match_operand:VF_AUTO 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + ;; ========================================================================= ;; == Ternary arithmetic ;; ========================================================================= diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c index d864b54229b..5575ece4599 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" @@ -7,30 +7,32 @@ #define SZ 128 -#define RUN(TYPE) \ - TYPE a##TYPE[SZ]; \ - for (int i = 0; i < SZ; i++) \ - { \ - if (i & 1) \ - a##TYPE[i] = i - 64; \ - else \ - a##TYPE[i] = i; \ - } \ - vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ - for (int i = 0; i < SZ; i++) \ - { \ - if (i & 1) \ - assert (a##TYPE[i] == abs (i - 64)); \ - else \ - assert (a##TYPE[i] == i); \ +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + a##TYPE[i] = i - 64; \ + else \ + a##TYPE[i] = i; \ + } \ + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + assert (a##TYPE[i] == __builtin_abs (i - 64)); \ + else \ + assert (a##TYPE[i] == i); \ } -#define RUN_ALL() \ - RUN(int8_t) \ - RUN(int16_t) \ - RUN(int32_t) \ - RUN(int64_t) +#define RUN_ALL() \ + RUN(int8_t) \ + RUN(int16_t) \ + RUN(int32_t) \ + RUN(int64_t) \ + RUN(float) \ + RUN(double) \ int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c index a8b92c9450f..dea790ccc2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c @@ -1,8 +1,9 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */ /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c index 2e7f0864ee7..b58f1aa3496 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c @@ -1,8 +1,9 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "abs-template.h" /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */ /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */ /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h index 882de9f4efb..08bd5b3629c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h @@ -6,7 +6,7 @@ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ { \ for (int i = 0; i < n; i++) \ - dst[i] = abs (a[i]); \ + dst[i] = __builtin_abs (a[i]); \ } #define TEST_TYPE2(TYPE) \ @@ -14,13 +14,24 @@ void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ { \ for (int i = 0; i < n; i++) \ - dst[i] = llabs (a[i]); \ + dst[i] = __builtin_llabs (a[i]); \ + } + +#define TEST_TYPE3(TYPE) \ + __attribute__((noipa)) \ + void vabs_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_fabs (a[i]); \ } #define TEST_ALL() \ TEST_TYPE(int8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(int32_t) \ - TEST_TYPE2(int64_t) + TEST_TYPE2(int64_t) \ + TEST_TYPE3(_Float16) \ + TEST_TYPE3(float) \ + TEST_TYPE3(double) \ TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c new file mode 100644 index 00000000000..65087d51665 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "abs-template.h" + +#include + +#define SZ 128 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + a##TYPE[i] = i - 64; \ + else \ + a##TYPE[i] = i; \ + } \ + vabs_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + { \ + if (i & 1) \ + assert (a##TYPE[i] == __builtin_abs (i - 64)); \ + else \ + assert (a##TYPE[i] == i); \ + } + + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c new file mode 100644 index 00000000000..01a518451e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +#include + +#define SZ 255 + +#define EPS 1e-5 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = (TYPE)i; \ + } \ + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs \ + (a##TYPE[i] - __builtin_sqrtf ((TYPE)i)) < EPS); \ + +#define RUN_ALL() \ + RUN(float) \ + RUN(double) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c new file mode 100644 index 00000000000..a1874c8f9f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly (which is also + included by the run test that might need to be linked without + the extension). */ +TEST_TYPE3(_Float16) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c new file mode 100644 index 00000000000..955621d4bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly (which is also + included by the run test that might need to be linked without + the extension). */ +TEST_TYPE3(_Float16) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h new file mode 100644 index 00000000000..314ea646bec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h @@ -0,0 +1,31 @@ +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrtf (a[i]); \ + } + +#define TEST_TYPE2(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrt (a[i]); \ + } + +#define TEST_TYPE3(TYPE) \ + __attribute__((noipa)) \ + void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_sqrtf16 (a[i]); \ + } + +#define TEST_ALL() \ + TEST_TYPE(float) \ + TEST_TYPE2(double) \ + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c new file mode 100644 index 00000000000..5849e486047 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vfsqrt-template.h" + +/* We cannot link this without the Zvfh extension so define + it here instead of in the template directly. */ +TEST_TYPE3(_Float16) + +#include + +#define SZ 255 + +#define EPS 1e-5 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = (TYPE)i; \ + } \ + vsqrt_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs \ + (a##TYPE[i] - __builtin_sqrtf ((TYPE)i)) < EPS); \ + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c index abeb50f21ea..f9fb126b3b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" @@ -13,7 +13,7 @@ { \ a##TYPE[i] = i - 127; \ } \ - vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ for (int i = 0; i < SZ; i++) \ assert (a##TYPE[i] == -(i - 127)); @@ -21,7 +21,9 @@ RUN(int8_t) \ RUN(int16_t) \ RUN(int32_t) \ - RUN(int64_t) + RUN(int64_t) \ + RUN(float) \ + RUN(double) \ int main () { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c index 69d9ebb0953..4a9ceb5faf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c index d2c2e17c13e..2c5e2bd2a0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ #include "vneg-template.h" /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h index 93e690f3cec..892d9d72c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h @@ -13,6 +13,9 @@ TEST_TYPE(int8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(int32_t) \ - TEST_TYPE(int64_t) + TEST_TYPE(int64_t) \ + TEST_TYPE(_Float16) \ + TEST_TYPE(float) \ + TEST_TYPE(double) \ TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c new file mode 100644 index 00000000000..64c965fea1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "vneg-template.h" + +#include + +#define SZ 255 + +#define RUN(TYPE) \ + TYPE a##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i - 127; \ + } \ + vneg_##TYPE (a##TYPE, a##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == -(i - 127)); + +#define RUN_ALL() \ + RUN(_Float16) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c index 08da48d0270..109fcbcaf00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c @@ -31,5 +31,19 @@ void f4 (_Float16 * __restrict a, _Float16 * __restrict b, int n) a[i] = a[i]/b[i]; } -/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when -march="*zvfhmin*". */ +void f6 (_Float16 * __restrict a, _Float16 * __restrict b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = __builtin_fabs (b[i]); +} + +void f7 (_Float16 * __restrict a, _Float16 * __restrict b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = __builtin_sqrtf (b[i]); +} + +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV/ABS/SQRTF auto-vectorization + when -march="*zvfhmin*" because the min variant of the extension only + provides loads, stores and conversions. */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" } } */ -- 2.40.1