Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV

[Jeff Law <jeffreyalaw@gmail.com>]

On 12/20/23 19:25, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to XFail the signbit-5 run test case for
> the RVV.  Given the case has one limitation like "This test does not
> work when the truth type does not match vector type." in the beginning
> of the test file.  Aka, the RVV vector truth type is not integer type.
> 
> The target board of riscv-sim like below will pick up `-march=rv64gcv`
> when building the run test elf. Thus, the RVV cannot bypass this test
> case like aarch64_sve with additional option `-march=armv8-a`.
> 
>    riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow
> 
> For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`.
But isn't that just going to turn this into an XPASS when vector is not 
enabled?

Looking at a recent rv64gc run of mine:

> PASS: gcc.dg/signbit-5.c (test for excess errors)
> PASS: gcc.dg/signbit-5.c execution test


Ideally we'd find a way to handle with and without vector.

jeff