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* [PATCH v2] xtensa: Make full transition to LRA
@ 2024-01-24  5:15 Max Filippov
  0 siblings, 0 replies; 9+ messages in thread
From: Max Filippov @ 2024-01-24  5:15 UTC (permalink / raw)
  To: gcc-patches; +Cc: Takayuki 'January June' Suwa

From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>

gcc/ChangeLog:

	* config/xtensa/constraints.md (R, T, U):
	Change define_constraint to define_memory_constraint.
	* config/xtensa/predicates.md (move_operand): Don't check that a
	constant pool operand size is a multiple of UNITS_PER_WORD.
	* config/xtensa/xtensa.cc
	(xtensa_lra_p, TARGET_LRA_P): Remove.
	(xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
	clause as it can no longer be true.
	(fixup_subreg_mem): Drop function.
	(xtensa_output_integer_literal_parts): Consider 16-bit wide
	constants.
	(xtensa_legitimate_constant_p): Add short-circuit path for
	integer load instructions. Don't check that mode size is
       	at least UNITS_PER_WORD.
	* config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
	rather reload_in_progress and reload_completed.
	(doloop_end): Drop operand 2.
	(movhi_internal): Add alternative loading constant from a
	literal pool.
	* config/xtensa/xtensa.opt (mlra): Change to no effect.
---
 gcc/config/xtensa/constraints.md | 26 ++++++------------
 gcc/config/xtensa/predicates.md  |  4 +--
 gcc/config/xtensa/xtensa.cc      | 46 +++++---------------------------
 gcc/config/xtensa/xtensa.md      | 15 +++++------
 gcc/config/xtensa/xtensa.opt     |  4 +--
 5 files changed, 24 insertions(+), 71 deletions(-)

diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md
index 5cade1db8ff1..dc6ffb5ba15c 100644
--- a/gcc/config/xtensa/constraints.md
+++ b/gcc/config/xtensa/constraints.md
@@ -123,29 +123,19 @@
       (and (match_code "const_int")
 	   (match_test "! xtensa_split1_finished_p ()"))))
 
-;; Memory constraints.  Do not use define_memory_constraint here.  Doing so
-;; causes reload to force some constants into the constant pool, but since
-;; the Xtensa constant pool can only be accessed with L32R instructions, it
-;; is always better to just copy a constant into a register.  Instead, use
-;; regular constraints but add a check to allow pseudos during reload.
+;; Memory constraints.
 
-(define_constraint "R"
+(define_memory_constraint "R"
  "Memory that can be accessed with a 4-bit unsigned offset from a register."
- (ior (and (match_code "mem")
-	   (match_test "smalloffset_mem_p (op)"))
-      (and (match_code "reg")
-	   (match_test "reload_in_progress
-			&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+ (and (match_code "mem")
+      (match_test "smalloffset_mem_p (op)")))
 
-(define_constraint "T"
+(define_memory_constraint "T"
  "Memory in a literal pool (addressable with an L32R instruction)."
  (and (match_code "mem")
       (match_test "!TARGET_CONST16 && constantpool_mem_p (op)")))
 
-(define_constraint "U"
+(define_memory_constraint "U"
  "Memory that is not in a literal pool."
- (ior (and (match_code "mem")
-	   (match_test "! constantpool_mem_p (op)"))
-      (and (match_code "reg")
-	   (match_test "reload_in_progress
-			&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
+ (and (match_code "mem")
+      (match_test "! constantpool_mem_p (op)")))
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index 672fb003a6c5..dd77911e3b70 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -143,9 +143,7 @@
 (define_predicate "move_operand"
   (ior
      (ior (match_operand 0 "register_operand")
-	  (and (match_operand 0 "memory_operand")
-	       (match_test "!constantpool_mem_p (op)
-			    || GET_MODE_SIZE (mode) % UNITS_PER_WORD == 0")))
+	  (match_operand 0 "memory_operand"))
      (ior (and (match_code "const_int")
 	       (match_test "(GET_MODE_CLASS (mode) == MODE_INT
 			     && xtensa_simm12b (INTVAL (op)))
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index a4f8e3e49d06..22b4416f48e4 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -115,7 +115,6 @@ static enum internal_test map_test_to_internal_test (enum rtx_code);
 static rtx gen_int_relational (enum rtx_code, rtx, rtx);
 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
 static rtx gen_conditional_move (enum rtx_code, machine_mode, rtx, rtx);
-static rtx fixup_subreg_mem (rtx);
 static struct machine_function * xtensa_init_machine_status (void);
 static rtx xtensa_legitimize_tls_address (rtx);
 static rtx xtensa_legitimize_address (rtx, rtx, machine_mode);
@@ -192,7 +191,6 @@ static void xtensa_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 				    HOST_WIDE_INT delta,
 				    HOST_WIDE_INT vcall_offset,
 				    tree function);
-static bool xtensa_lra_p (void);
 
 static rtx xtensa_delegitimize_address (rtx);
 
@@ -286,9 +284,6 @@ static rtx xtensa_delegitimize_address (rtx);
 #undef TARGET_CANNOT_FORCE_CONST_MEM
 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
 
-#undef TARGET_LRA_P
-#define TARGET_LRA_P xtensa_lra_p
-
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P	xtensa_legitimate_address_p
 
@@ -1333,35 +1328,10 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
 
   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 
-  /* During reload we don't want to emit (subreg:X (mem:Y)) since that
-     instruction won't be recognized after reload, so we remove the
-     subreg and adjust mem accordingly.  */
-  if (reload_in_progress)
-    {
-      operands[0] = fixup_subreg_mem (operands[0]);
-      operands[1] = fixup_subreg_mem (operands[1]);
-    }
   return 0;
 }
 
 
-static rtx
-fixup_subreg_mem (rtx x)
-{
-  if (GET_CODE (x) == SUBREG
-      && GET_CODE (SUBREG_REG (x)) == REG
-      && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
-    {
-      rtx temp =
-	gen_rtx_SUBREG (GET_MODE (x),
-			reg_equiv_mem (REGNO (SUBREG_REG (x))),
-			SUBREG_BYTE (x));
-      x = alter_subreg (&temp, true);
-    }
-  return x;
-}
-
-
 /* Check if an incoming argument in a7 is expected to be used soon and
    if OPND is a register or register pair that includes a7.  If so,
    create a new pseudo and copy a7 into that pseudo at the very
@@ -2355,7 +2325,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict,
 			     code_helper)
 {
   /* Allow constant pool addresses.  */
-  if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
+  if (mode != BLKmode
       && ! TARGET_CONST16 && constantpool_address_p (addr)
       && ! xtensa_tls_referenced_p (addr))
     return true;
@@ -3280,7 +3250,7 @@ xtensa_output_integer_literal_parts (FILE *file, rtx x, int size)
       fputs (", ", file);
       xtensa_output_integer_literal_parts (file, second, size / 2);
     }
-  else if (size == 4)
+  else if (size == 4 || size == 2)
     {
       output_addr_const (file, x);
     }
@@ -4952,6 +4922,10 @@ xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
 static bool
 xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
 {
+  if (CONST_INT_P (x))
+    return TARGET_AUTO_LITPOOLS || TARGET_CONST16
+	   || xtensa_simm12b (INTVAL (x));
+
   return !xtensa_tls_referenced_p (x);
 }
 
@@ -5393,12 +5367,4 @@ xtensa_delegitimize_address (rtx op)
   return op;
 }
 
-/* Implement TARGET_LRA_P.  */
-
-static bool
-xtensa_lra_p (void)
-{
-  return TARGET_LRA;
-}
-
 #include "gt-xtensa.h"
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 20af1cbfbd03..184b44e45f49 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1328,8 +1328,8 @@
 })
 
 (define_insn "movhi_internal"
-  [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
-	(match_operand:HI 1 "move_operand" "M,d,r,I,Y,U,r,*A,*r"))]
+  [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,a,U,*a,*A")
+	(match_operand:HI 1 "move_operand" "M,d,r,I,Y,T,U,r,*A,*r"))]
   "xtensa_valid_move (HImode, operands)"
   "@
    movi.n\t%0, %x1
@@ -1337,13 +1337,14 @@
    mov\t%0, %1
    movi\t%0, %x1
    movi\t%0, %1
+   %v1l32r\t%0, %1
    %v1l16ui\t%0, %1
    %v0s16i\t%1, %0
    rsr\t%0, ACCLO
    wsr\t%1, ACCLO"
-  [(set_attr "type"	"move,move,move,move,move,load,store,rsr,wsr")
+  [(set_attr "type"	"move,move,move,move,move,load,load,store,rsr,wsr")
    (set_attr "mode"	"HI")
-   (set_attr "length"	"2,2,3,3,3,3,3,3,3")])
+   (set_attr "length"	"2,2,3,3,3,3,3,3,3,3")])
 
 ;; 8-bit Integer moves
 
@@ -1420,7 +1421,7 @@
   if ((!register_operand (operands[0], SFmode)
        && !register_operand (operands[1], SFmode))
       || (FP_REG_P (xt_true_regnum (operands[0]))
-	  && !(reload_in_progress | reload_completed)
+	  && can_create_pseudo_p ()
 	  && (constantpool_mem_p (operands[1])
 	      || CONSTANT_P (operands[1]))))
     operands[1] = force_reg (SFmode, operands[1]);
@@ -2368,14 +2369,12 @@
 	      (set (match_dup 0)
 		   (plus:SI (match_dup 0)
 			    (const_int -1)))
-	      (unspec [(const_int 0)] UNSPEC_LSETUP_END)
-	      (clobber (match_dup 2))])] ; match_scratch
+	      (unspec [(const_int 0)] UNSPEC_LSETUP_END)])]
   "TARGET_LOOPS && optimize"
 {
   /* The loop optimizer doesn't check the predicates... */
   if (GET_MODE (operands[0]) != SImode)
     FAIL;
-  operands[2] = gen_rtx_SCRATCH (SImode);
 })
 
 \f
diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt
index f16b53bf409f..19c9bd37a187 100644
--- a/gcc/config/xtensa/xtensa.opt
+++ b/gcc/config/xtensa/xtensa.opt
@@ -38,8 +38,8 @@ Target RejectNegative Joined UInteger Var(xtensa_extra_l32r_costs) Init(0)
 Set extra memory access cost for L32R instruction, in clock-cycle units.
 
 mlra
-Target Mask(LRA)
-Use LRA instead of reload (transitional).
+Target Ignore
+Does nothing.  Preserved for backward compatibility.
 
 mtarget-align
 Target
-- 
2.39.2


^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-10-20 16:36 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <91ddbcb5-67e2-2c30-a81e-6b20e3c8e1a4.ref@yahoo.co.jp>
2023-05-08 13:38 ` [PATCH] xtensa: Make full transition to LRA Takayuki 'January June' Suwa
2023-05-08 13:43   ` Richard Biener
2023-05-08 14:44     ` [PATCH v2] " Takayuki 'January June' Suwa
2023-05-08 22:26       ` Jeff Law
2025-10-09 21:33         ` [PATCH 3/3] xtensa: Make all memory constraints special Takayuki 'January June' Suwa
2025-10-20 16:36           ` Max Filippov
2023-05-10  9:10   ` [PATCH] xtensa: Make full transition to LRA Max Filippov
2024-01-24  5:07     ` Max Filippov
2024-01-24  5:15 [PATCH v2] " Max Filippov

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