From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 116536 invoked by alias); 14 Dec 2017 00:37:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 116511 invoked by uid 89); 14 Dec 2017 00:37:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_PASS,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Dec 2017 00:37:01 +0000 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CB158B5AD; Thu, 14 Dec 2017 00:37:00 +0000 (UTC) Received: from localhost.localdomain (ovpn-112-2.rdu2.redhat.com [10.10.112.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id 041F060A9D; Thu, 14 Dec 2017 00:36:59 +0000 (UTC) Subject: Re: Add support for bitwise reductions To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org References: <87tvxtz0xc.fsf@linaro.org> <87lgiyp4i5.fsf@linaro.org> From: Jeff Law Message-ID: <43b3bee8-e2ac-1ad8-549a-13c9e47b6f1c@redhat.com> Date: Thu, 14 Dec 2017 00:37:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <87lgiyp4i5.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2017-12/txt/msg00869.txt.bz2 On 11/22/2017 11:12 AM, Richard Sandiford wrote: > Richard Sandiford writes: >> This patch adds support for the SVE bitwise reduction instructions >> (ANDV, ORV and EORV). It's a fairly mechanical extension of existing >> REDUC_* operators. >> >> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu >> and powerpc64le-linux-gnu. > > Here's an updated version that applies on top of the recent > removal of REDUC_*_EXPR. Tested as before. > > Thanks, > Richard > > > 2017-11-22 Richard Sandiford > Alan Hayward > David Sherwood > > gcc/ > * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab) > (reduc_xor_scal_optab): New optabs. > * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m}) > (reduc_xor_scal_@var{m}): Document. > * doc/sourcebuild.texi (vect_logical_reduc): Likewise. > * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New > internal functions. > * fold-const-call.c (fold_const_call): Handle them. > * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new > internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR. > * config/aarch64/aarch64-sve.md (reduc__scal_): > (*reduc__scal_): New patterns. > * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV) > (UNSPEC_XORV): New unspecs. > (optab): Add entries for them. > (BITWISEV): New int iterator. > (bit_reduc_op): New int attributes. > > gcc/testsuite/ > * lib/target-supports.exp (check_effective_target_vect_logical_reduc): > New proc. > * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc > and add an associated scan-dump test. Prevent vectorization > of the first two loops. > * gcc.dg/vect/vect-reduc-or_2.c: Likewise. > * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions. > * gcc.target/aarch64/sve_reduc_2.c: Likewise. > * gcc.target/aarch64/sve_reduc_1_run.c: Likewise. > (INIT_VECTOR): Tweak initial value so that some bits are always set. > * gcc.target/aarch64/sve_reduc_2_run.c: Likewise. OK. Jeff