[PATCH-3v3, rs6000] Implement optab_isnormal for SFDF and IEEE128

[PATCH-3v3, rs6000] Implement optab_isnormal for SFDF and IEEE128

[HAO CHEN GUI]

Hi,
  This patch implemented optab_isnormal for SFDF and IEEE128 by
test data class instructions.

  Compared with previous version, the main change is to narrow
down the predict for float operand according to review's advice.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652130.html

  Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is it OK for trunk?

Thanks
Gui Haochen

ChangeLog
rs6000: Implement optab_isnormal for SFDF and IEEE128

gcc/
	PR target/97786
	* config/rs6000/vsx.md (isnormal<mode>2 for SFDF): New expand.
	(isnormal<mode>2 for IEEE128): New expand.

gcc/testsuite/
	PR target/97786
	* gcc.target/powerpc/pr97786-7.c: New test.
	* gcc.target/powerpc/pr97786-8.c: New test.

patch.diff
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 95214d732f0..d4d98543912 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5353,6 +5353,28 @@ (define_expand "isfinite<mode>2"
   DONE;
 })

+(define_expand "isnormal<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:SFDF 1 "vsx_register_operand"))]
+  "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+{
+  rtx tmp = gen_reg_rtx (SImode);
+  emit_insn (gen_xststdc<sd>p (tmp, operands[1], GEN_INT (0x7f)));
+  emit_insn (gen_xorsi3 (operands[0], tmp, const1_rtx));
+  DONE;
+})
+
+(define_expand "isnormal<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:IEEE128 1 "vsx_register_operand"))]
+  "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+{
+  rtx tmp = gen_reg_rtx (SImode);
+  emit_insn (gen_xststdcqp_<mode> (tmp, operands[1], GEN_INT (0x7f)));
+  emit_insn (gen_xorsi3 (operands[0], tmp, const1_rtx));
+  DONE;
+})
+
 ;; The VSX Scalar Test Negative Quad-Precision
 (define_expand "xststdcnegqp_<mode>"
   [(set (match_dup 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-7.c b/gcc/testsuite/gcc.target/powerpc/pr97786-7.c
new file mode 100644
index 00000000000..2df472e35d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+
+int test1 (double x)
+{
+  return __builtin_isnormal (x);
+}
+
+int test2 (float x)
+{
+  return __builtin_isnormal (x);
+}
+
+/* { dg-final { scan-assembler-not {\mfcmp} } } */
+/* { dg-final { scan-assembler-times {\mxststdcsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxststdcdp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-8.c b/gcc/testsuite/gcc.target/powerpc/pr97786-8.c
new file mode 100644
index 00000000000..00478dbf3ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-8.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ppc_float128_hw } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -mabi=ieeelongdouble -Wno-psabi" } */
+
+int test1 (long double x)
+{
+  return __builtin_isnormal (x);
+}
+
+/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
+/* { dg-final { scan-assembler {\mxststdcqp\M} } } */