Stricter implicit conversions between vectors, revised patch

Stricter implicit conversions between vectors, revised patch

[Mark Shinwell]

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This patch is a revised version of the one in the thread "Patch for stricter
implicit conversions between vectors" back in November.  It addresses
recent concerns raised by Andrew Pinski, removing unnecessary modifications
from altivec.h and using comptypes from vector_types_convertible_p.  It also
adds documentation for -flax-vector-conversions and correctly fixes up
DejaGNU directives for certain testcases.

Whilst doing these modifications I noticed that comptypes_internal contains
logic that I believe needs updating as well; see the patch below.  Here I
have opted to define that compatibility and implicit convertibility for
vector types coincide, which I think is reasonable given how implicit
convertibility for these vector types is now checked (see patch).

Paulo, there is an outstanding modification to altivec.h -- see below -- of
which I am suspicious.  For some reason __builtin_altivec_vcmpgefp is
still being defined as returning vector signed int even though, as far as
I can see, it should be returning vector bool int as required for the
return type of vec_cmple.  Do you know what might be going on here (and
is it reasonable in any case to define vec_cmple in terms of
__builtin_vec_cmpge)?

This patch exhibits no changes in testsuite results with all default
languages on x86_64-unknown-linux-gnu.  I haven't quite reached this
on powerpc64-unknown-linux-gnu but I think the only outstanding problem
is due to this vcmpgefp issue.

Is this ok to apply once we have resolved that and obtained clean results
on powerpc64?

Mark

--


2006-12-21  Mark Shinwell  <shinwell@codesourcery.com>

	gcc/
	* c.opt: Add -flax-vector-conversions.
	* c-typeck.c (convert_for_assignment): Pass flag to
	vector_types_convertible_p to allow emission of note.
	(digest_init): Likewise.
	(comptypes_internal): Use vector_types_convertible_p.
	* c-opts.c: Handle -flax-vector-conversions.
	* c-common.c (flag_lax_vector_conversions): New.
	(vector_types_convertible_p): Unless -flax-vector conversions
	has been passed, disallow conversions between vectors with
	differing numbers of subparts and/or element types.  If such
	a conversion is disallowed, possibly emit a note on the first
	occasion only to inform the user of -flax-vector-conversions.
	The new last argument specifies this.
	* c-common.h (flag_lax_vector_conversions): New.
	(vector_types_convertible_p): Add extra argument.
	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Use
	char_type_node for V*QI type vectors.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins):
	Update to satisfy new typechecking rules.
	* config/rs6000/altivec.h (vec_cmple): Use vec_cmpge.
	* doc/invoke.texi (C Dialect Options): Document
	-flax-vector-conversions.

	gcc/cp/
	* call.c (standard_conversion): Pass flag to
	vector_types_convertible_p to disallow emission of note.
	* typeck.c (convert_for_assignment): Pass flag to
	vector_types_convertible_p to allow emission of note.
	(ptr_reasonably_similar): Pass flag to vector_types_convertible_p
	to disallow emission of note.

	gcc/testsuite/
	* gcc.target/i386/20020531-1.c: Use "char" not "unsigned char"
	in __v8qi typedef.
	* gcc.target/powerpc/altivec-vec-merge.c (foo): Add casts.
	* gcc.dg/simd-1.c: Update dg-error directives to reflect new
	compiler behaviour.
	* gcc.dg/simd-5.c: Likewise.
	* gcc.dg/simd-6.c: Likewise.
	* g++.dg/conversion/simd1.C: Likewise.
	* g++.dg/conversion/simd3.C: Likewise.
	* g++.dg/ext/attribute-test-2.C (data): Add "vs" member.
	(main): Use it.

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Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 120074)
+++ gcc/doc/invoke.texi	(working copy)
@@ -168,7 +168,7 @@ in the following sections.
 -fno-asm  -fno-builtin  -fno-builtin-@var{function} @gol
 -fhosted  -ffreestanding -fopenmp -fms-extensions @gol
 -trigraphs  -no-integrated-cpp  -traditional  -traditional-cpp @gol
--fallow-single-precision  -fcond-mismatch @gol
+-fallow-single-precision  -fcond-mismatch -flax-vector-conversions @gol
 -fsigned-bitfields  -fsigned-char @gol
 -funsigned-bitfields  -funsigned-char}
 
@@ -1378,6 +1378,12 @@ Allow conditional expressions with misma
 third arguments.  The value of such an expression is void.  This option
 is not supported for C++.
 
+@item -flax-vector-conversions
+@opindex flax-vector-conversions
+Allow implicit conversions between vectors with differing numbers of
+elements and/or incompatible element types.  This option should not be
+used for new code.
+
 @item -funsigned-char
 @opindex funsigned-char
 Let the type @code{char} be unsigned, like @code{unsigned char}.
Index: gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c	(revision 120074)
+++ gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c	(working copy)
@@ -96,7 +96,7 @@ void foo(char *bS, char *bS_edge, int fi
     v6   = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3);
   }
   else  {
-    v4 = v5 = v6 = vec_nor (v_zero, v_zero);
+    v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
@@ -335,7 +335,7 @@ void foo(char *bS, char *bS_edge, int fi
     v10  = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11);
   }
   else  {
-    v8 = v9 = v10 = vec_nor (v_zero, v_zero);
+    v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
Index: gcc/testsuite/gcc.target/i386/20020531-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/20020531-1.c	(revision 120074)
+++ gcc/testsuite/gcc.target/i386/20020531-1.c	(working copy)
@@ -4,7 +4,7 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
 /* { dg-options "-O2 -mmmx" } */
 
-typedef unsigned char __v8qi __attribute__ ((vector_size (8)));
+typedef char __v8qi __attribute__ ((vector_size (8)));
 extern void abort (void);
 extern void exit (int);
 
Index: gcc/testsuite/gcc.dg/simd-5.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-5.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-5.c	(working copy)
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit.*conversions between vectors with differing.*element types or numbers of subparts.*incompatible types in initialization" } */
Index: gcc/testsuite/gcc.dg/simd-6.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-6.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-6.c	(working copy)
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit.*conversions between vectors with differing.*element types or numbers of subparts.*incompatible types in initialization" } */
Index: gcc/testsuite/gcc.dg/simd-1.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-1.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-1.c	(working copy)
@@ -32,7 +32,7 @@ hanneke ()
   e = (typeof (e)) a;
 
   /* Different signed SIMD assignment.  */
-  f = a;
+  f = a; /* { dg-error "use -flax-vector-conversions to permit.*conversions between vectors with differing.*element types or numbers of subparts.*35: error: incompatible types in assignment" } */
 
   /* Casted different signed SIMD assignment.  */
   f = (uv4si) a;
Index: gcc/testsuite/g++.dg/conversion/simd1.C
===================================================================
--- gcc/testsuite/g++.dg/conversion/simd1.C	(revision 120074)
+++ gcc/testsuite/g++.dg/conversion/simd1.C	(working copy)
@@ -5,9 +5,9 @@
 
 #define vector __attribute__((vector_size(16)))
 
-vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "vld" } */
 /* { dg-warning "vector returned by ref" "" { target { powerpc*-*-linux* && ilp32 } }  8 } */
-vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "vld" } */
 
 extern int i;
 extern vector signed short vss;
@@ -17,7 +17,7 @@ extern const vector signed short *cvssp;
 
 void foo ()
 {
-  vss = vld(i, vscp);        /* { dg-error "no match" } */
+  vss = vld(i, vscp);        /* { dg-error "no matching function for call" } */
:1
   vss = vld(i, vssp);
   vss = vld(i, cvssp);
 }
Index: gcc/testsuite/g++.dg/conversion/simd3.C
===================================================================
--- gcc/testsuite/g++.dg/conversion/simd3.C	(revision 120074)
+++ gcc/testsuite/g++.dg/conversion/simd3.C	(working copy)
@@ -10,6 +10,6 @@ unsigned int __attribute__((vector_size(
 void foo()
 {
 	b + d; /* { dg-error "invalid operands to binary" } */
-	d += e;
+	d += e; /* { dg-error "use -flax-vector-conversions to permit.*conversions between vectors with differing.*element types or numbers of subparts.*cannot convert 'unsigned int __vector__' to 'int __vector__' in assignment" } */
 	d2 += d;
 }
Index: gcc/testsuite/g++.dg/ext/attribute-test-2.C
===================================================================
--- gcc/testsuite/g++.dg/ext/attribute-test-2.C	(revision 120074)
+++ gcc/testsuite/g++.dg/ext/attribute-test-2.C	(working copy)
@@ -15,8 +15,8 @@ public:
      return (__attribute__((vector_size(16))) short) vec;
    }
 
-   operator __attribute__((vector_size(16))) int (void) {
-     return (__attribute__((vector_size(16))) int) vec1;
+   operator __attribute__((vector_size(16))) unsigned int (void) {
+     return (__attribute__((vector_size(16))) unsigned int) vec1;
    }
 
    vector_holder () {
@@ -30,6 +30,7 @@ public:
 union u {
               char f[16];
               vector unsigned int v;
+              vector short vs;
 } data;
 
 
@@ -37,10 +38,10 @@ vector_holder vh;
 
 int main()
 {
-  data.v = (__attribute__((vector_size(16))) short) vh;
+  data.vs = (__attribute__((vector_size(16))) short) vh;
   if (data.f[0] != 'a' || data.f[15] != 'd')
     abort(); 
-  data.v = (__attribute__((vector_size(16))) int) vh;
+  data.v = (__attribute__((vector_size(16))) unsigned int) vh;
   if (data.f[0] != 'm' || data.f[15] != 'p')
     abort(); 
 
Index: gcc/cp/typeck.c
===================================================================
--- gcc/cp/typeck.c	(revision 120074)
+++ gcc/cp/typeck.c	(working copy)
@@ -6218,7 +6218,7 @@ convert_for_assignment (tree type, tree 
   coder = TREE_CODE (rhstype);
 
   if (TREE_CODE (type) == VECTOR_TYPE && coder == VECTOR_TYPE
-      && vector_types_convertible_p (type, rhstype))
+      && vector_types_convertible_p (type, rhstype, true))
     return convert (type, rhs);
 
   if (rhs == error_mark_node || rhstype == error_mark_node)
@@ -6774,7 +6774,7 @@ ptr_reasonably_similar (tree to, tree fr
 	continue;
 
       if (TREE_CODE (to) == VECTOR_TYPE
-	  && vector_types_convertible_p (to, from))
+	  && vector_types_convertible_p (to, from, false))
 	return 1;
 
       if (TREE_CODE (to) == INTEGER_TYPE
Index: gcc/cp/call.c
===================================================================
--- gcc/cp/call.c	(revision 120074)
+++ gcc/cp/call.c	(working copy)
@@ -842,7 +842,7 @@ standard_conversion (tree to, tree from,
 	conv->rank = cr_promotion;
     }
   else if (fcode == VECTOR_TYPE && tcode == VECTOR_TYPE
-	   && vector_types_convertible_p (from, to))
+	   && vector_types_convertible_p (from, to, false))
     return build_conv (ck_std, to, conv);
   else if (!(flags & LOOKUP_CONSTRUCTOR_CALLABLE)
 	   && IS_AGGR_TYPE (to) && IS_AGGR_TYPE (from)
Index: gcc/c.opt
===================================================================
--- gcc/c.opt	(revision 120074)
+++ gcc/c.opt	(working copy)
@@ -571,6 +571,10 @@ Inject friend functions into enclosing n
 flabels-ok
 C++ ObjC++
 
+flax-vector-conversions
+C ObjC C++ ObjC++
+Allow implicit conversions between vectors with differing numbers of subparts and/or differing element types.
+
 fms-extensions
 C ObjC C++ ObjC++
 Don't warn about uses of Microsoft extensions
Index: gcc/c-typeck.c
===================================================================
--- gcc/c-typeck.c	(revision 120074)
+++ gcc/c-typeck.c	(working copy)
@@ -918,8 +918,9 @@ comptypes_internal (tree type1, tree typ
       break;
 
     case VECTOR_TYPE:
-      val = TYPE_VECTOR_SUBPARTS (t1) == TYPE_VECTOR_SUBPARTS (t2)
-	    && comptypes_internal (TREE_TYPE (t1), TREE_TYPE (t2));
+      /* We define compatibility for vector types to coincide with implicit
+	 convertibility.  */
+      val = (vector_types_convertible_p (t1, t2, false) ? 1 : 0);
       break;
 
     default:
@@ -4600,7 +4601,7 @@ digest_init (tree type, tree init, bool 
      below and handle as a constructor.  */
   if (code == VECTOR_TYPE
       && TREE_CODE (TREE_TYPE (inside_init)) == VECTOR_TYPE
-      && vector_types_convertible_p (TREE_TYPE (inside_init), type)
+      && vector_types_convertible_p (TREE_TYPE (inside_init), type, true)
       && TREE_CONSTANT (inside_init))
     {
       if (TREE_CODE (inside_init) == VECTOR_CST
Index: gcc/c-opts.c
===================================================================
--- gcc/c-opts.c	(revision 120074)
+++ gcc/c-opts.c	(working copy)
@@ -705,6 +705,10 @@ c_common_handle_option (size_t scode, co
       flag_implicit_templates = value;
       break;
 
+    case OPT_flax_vector_conversions:
+      flag_lax_vector_conversions = value;
+      break;
+
     case OPT_fms_extensions:
       flag_ms_extensions = value;
       break;
Index: gcc/c-common.c
===================================================================
--- gcc/c-common.c	(revision 120074)
+++ gcc/c-common.c	(working copy)
@@ -254,6 +254,10 @@ int flag_short_double;
 
 int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 int flag_ms_extensions;
 
@@ -1072,19 +1076,40 @@ check_main_parameter_types (tree decl)
    pedwarn ("%q+D takes only zero or two arguments", decl);
 }
 
- 
-/* Nonzero if vector types T1 and T2 can be converted to each other
-   without an explicit cast.  */
-int
-vector_types_convertible_p (tree t1, tree t2)
+/* True if vector types T1 and T2 can be converted to each other
+   without an explicit cast.  If EMIT_LAX_NOTE is true, and T1 and T2
+   can only be converted with -flax-vector-conversions yet that is not
+   in effect, emit a note telling the user about that option if such
+   a note has not previously been emitted.  */
+bool
+vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note)
 {
-  return targetm.vector_opaque_p (t1)
-	 || targetm.vector_opaque_p (t2)
-	 || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
-	     && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
-		 TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
-	     && INTEGRAL_TYPE_P (TREE_TYPE (t1))
-		== INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+  static bool emitted_lax_note = false;
+  bool convertible_lax =
+    targetm.vector_opaque_p (t1)
+    || targetm.vector_opaque_p (t2)
+    || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
+        && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
+           TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
+       && INTEGRAL_TYPE_P (TREE_TYPE (t1))
+          == INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+
+  if (!convertible_lax || flag_lax_vector_conversions)
+    return convertible_lax;
+
+  if (TYPE_VECTOR_SUBPARTS (t1) == TYPE_VECTOR_SUBPARTS (t2)
+      && comptypes (TREE_TYPE (t1), TREE_TYPE (t2)))
+    return true;
+
+  if (emit_lax_note && !emitted_lax_note)
+    {
+      emitted_lax_note = true;
+      inform ("use -flax-vector-conversions to permit");
+      inform ("conversions between vectors with differing");
+      inform ("element types or numbers of subparts");
+    }
+
+  return false;
 }
 
 /* Warns if the conversion of EXPR to TYPE may alter a value.
Index: gcc/c-common.h
===================================================================
--- gcc/c-common.h	(revision 120074)
+++ gcc/c-common.h	(working copy)
@@ -392,6 +392,10 @@ extern int flag_short_double;
 
 extern int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+extern int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 extern int flag_ms_extensions;
 
@@ -800,7 +804,7 @@ extern tree finish_label_address_expr (t
 extern tree lookup_label (tree);
 extern tree lookup_name (tree);
 
-extern int vector_types_convertible_p (tree t1, tree t2);
+extern bool vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note);
 
 extern rtx c_expand_expr (tree, rtx, enum machine_mode, int, rtx *);
 
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	(revision 120074)
+++ gcc/config/i386/i386.c	(working copy)
@@ -15911,7 +15911,7 @@ ix86_init_mmx_sse_builtins (void)
   const struct builtin_description * d;
   size_t i;
 
-  tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
+  tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
   tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
   tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
   tree V2DI_type_node
@@ -15920,7 +15920,7 @@ ix86_init_mmx_sse_builtins (void)
   tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
   tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
   tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
-  tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
+  tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
   tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
 
   tree pchar_type_node = build_pointer_type (char_type_node);
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c	(revision 120074)
+++ gcc/config/rs6000/rs6000-c.c	(working copy)
@@ -224,17 +224,17 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
@@ -242,17 +242,17 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
@@ -260,11 +260,11 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 
   /* Binary AltiVec builtins.  */
   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
@@ -578,31 +578,23 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
@@ -620,29 +612,29 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
Index: gcc/config/rs6000/altivec.h
===================================================================
--- gcc/config/rs6000/altivec.h	(revision 120074)
+++ gcc/config/rs6000/altivec.h	(working copy)
@@ -402,7 +402,7 @@ __altivec_scalar_pred(vec_any_nle,
 #undef __altivec_binary_pred
 #else
 #define vec_cmplt(a1, a2) __builtin_vec_cmpgt ((a2), (a1))
-#define vec_cmple(a1, a2) __builtin_altivec_vcmpgefp ((a2), (a1))
+#define vec_cmple(a1, a2) __builtin_vec_cmpge ((a2), (a1))
 
 #define vec_all_in(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ, (a1), (a2))
 #define vec_any_out(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ_REV, (a1), (a2))

Re: Stricter implicit conversions between vectors, revised patch

[Paolo Bonzini]

> Paulo, there is an outstanding modification to altivec.h -- see below -- of
> which I am suspicious.  For some reason __builtin_altivec_vcmpgefp is
> still being defined as returning vector signed int even though, as far as
> I can see, it should be returning vector bool int as required for the
> return type of vec_cmple.

Your AltiVec changes seem ok to me; see PR30210 (where you're already 
CCed anyway) for the gory details about __builtin_vec_* versus 
__builtin_altivec_* and why __builtin_altivec_vcmpgefp does not return a 
vector bool int.

So, I think your patch is correct, except that you also have to change 
the corresponding C++ code, which is quite wrong (predicates are defined 
as templates, and this has let a wrong name through):

  __altivec_binary_pred(vec_cmple,
-  __builtin_altivec_cmpge (a2, a1))
+  __builtin_vec_cmpge (a2, a1))

> This patch exhibits no changes in testsuite results with all default
> languages on x86_64-unknown-linux-gnu.  I haven't quite reached this
> on powerpc64-unknown-linux-gnu but I think the only outstanding problem
> is due to this vcmpgefp issue.

What is this problem?

Paolo

Re: Stricter implicit conversions between vectors, revised patch

[Mark Shinwell]

Paolo Bonzini wrote:
> [...] why __builtin_altivec_vcmpgefp does not return a 
> vector bool int.

Ah, so that applies for vcmpgefp as well, ok.

> So, I think your patch is correct, except that you also have to change 
> the corresponding C++ code, which is quite wrong (predicates are defined 
> as templates, and this has let a wrong name through):
> 
>  __altivec_binary_pred(vec_cmple,
> -  __builtin_altivec_cmpge (a2, a1))
> +  __builtin_vec_cmpge (a2, a1))

I did wonder about that one, but failed to mention it in the mail :-)
Will fix.

>> This patch exhibits no changes in testsuite results with all default
>> languages on x86_64-unknown-linux-gnu.  I haven't quite reached this
>> on powerpc64-unknown-linux-gnu but I think the only outstanding problem
>> is due to this vcmpgefp issue.
> 
> What is this problem?

Given what you say, I believe there is no problem.  I'll run the testsuite
again; it looks like we are finally there.

Thanks,
Mark

Re: Stricter implicit conversions between vectors, revised patch

[Mark Shinwell]

Mark Shinwell wrote:
>> What is this problem?
> 
> Given what you say, I believe there is no problem.  I'll run the testsuite
> again; it looks like we are finally there.

...but not quite.  Having just been discussing this with Joseph Myers it
looks like the existing compatibility rules are still in fact correct, and
another nuance has been pointed out: there shouldn't be multiple "inform"
calls about -flax-vector-conversions for i18n reasons.

Mark

Re: Stricter implicit conversions between vectors, revised patch

[Mark Shinwell]

[-- Attachment #1: Type: text/plain, Size: 2882 bytes --]

Mark Shinwell wrote:
> Mark Shinwell wrote:
>>> What is this problem?
>>
>> Given what you say, I believe there is no problem.  I'll run the 
>> testsuite
>> again; it looks like we are finally there.
> 
> ...but not quite.  Having just been discussing this with Joseph Myers it
> looks like the existing compatibility rules are still in fact correct, and
> another nuance has been pointed out: there shouldn't be multiple "inform"
> calls about -flax-vector-conversions for i18n reasons.

These have now been sorted.  This patch has no regressions on
x86_64-unknown-linux-gnu and powerpc64-unknown-linux-gnu.  OK to apply?

Mark

--


2006-12-23  Mark Shinwell  <shinwell@codesourcery.com>

         gcc/
         * c.opt: Add -flax-vector-conversions.
         * c-typeck.c (convert_for_assignment): Pass flag to
         vector_types_convertible_p to allow emission of note.
         (digest_init): Likewise.
         * c-opts.c: Handle -flax-vector-conversions.
         * c-common.c (flag_lax_vector_conversions): New.
         (vector_types_convertible_p): Unless -flax-vector conversions
         has been passed, disallow conversions between vectors with
         differing numbers of subparts and/or element types.  If such
         a conversion is disallowed, possibly emit a note on the first
         occasion only to inform the user of -flax-vector-conversions.
         The new last argument specifies this.
         * c-common.h (flag_lax_vector_conversions): New.
         (vector_types_convertible_p): Add extra argument.
         * config/i386/i386.c (ix86_init_mmx_sse_builtins): Use
         char_type_node for V*QI type vectors.
         * config/rs6000/rs6000-c.c (altivec_overloaded_builtins):
         Update to satisfy new typechecking rules.
         * config/rs6000/altivec.h (vec_cmple): Use vec_cmpge, for both
	C and C++ variants.
         * doc/invoke.texi (C Dialect Options): Document
         -flax-vector-conversions.

         gcc/cp/
         * call.c (standard_conversion): Pass flag to
         vector_types_convertible_p to disallow emission of note.
         * typeck.c (convert_for_assignment): Pass flag to
         vector_types_convertible_p to allow emission of note.
         (ptr_reasonably_similar): Pass flag to vector_types_convertible_p
         to disallow emission of note.

         gcc/testsuite/
         * gcc.target/i386/20020531-1.c: Use "char" not "unsigned char"
         in __v8qi typedef.
         * gcc.target/powerpc/altivec-vec-merge.c (foo): Add casts.
         * gcc.dg/simd-1.c: Update dg-error directives to reflect new
         compiler behaviour.
         * gcc.dg/simd-5.c: Likewise.
         * gcc.dg/simd-6.c: Likewise.
         * g++.dg/conversion/simd1.C: Likewise.
         * g++.dg/conversion/simd3.C: Likewise.
         * g++.dg/ext/attribute-test-2.C (data): Add "vs" member.
         (main): Use it.

[-- Attachment #2: vector-tightening.patch --]
[-- Type: text/plain, Size: 24563 bytes --]

Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 120074)
+++ gcc/doc/invoke.texi	(working copy)
@@ -168,7 +168,7 @@ in the following sections.
 -fno-asm  -fno-builtin  -fno-builtin-@var{function} @gol
 -fhosted  -ffreestanding -fopenmp -fms-extensions @gol
 -trigraphs  -no-integrated-cpp  -traditional  -traditional-cpp @gol
--fallow-single-precision  -fcond-mismatch @gol
+-fallow-single-precision  -fcond-mismatch -flax-vector-conversions @gol
 -fsigned-bitfields  -fsigned-char @gol
 -funsigned-bitfields  -funsigned-char}
 
@@ -1378,6 +1378,12 @@ Allow conditional expressions with misma
 third arguments.  The value of such an expression is void.  This option
 is not supported for C++.
 
+@item -flax-vector-conversions
+@opindex flax-vector-conversions
+Allow implicit conversions between vectors with differing numbers of
+elements and/or incompatible element types.  This option should not be
+used for new code.
+
 @item -funsigned-char
 @opindex funsigned-char
 Let the type @code{char} be unsigned, like @code{unsigned char}.
Index: gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c	(revision 120074)
+++ gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c	(working copy)
@@ -96,7 +96,7 @@ void foo(char *bS, char *bS_edge, int fi
     v6   = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3);
   }
   else  {
-    v4 = v5 = v6 = vec_nor (v_zero, v_zero);
+    v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
@@ -335,7 +335,7 @@ void foo(char *bS, char *bS_edge, int fi
     v10  = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11);
   }
   else  {
-    v8 = v9 = v10 = vec_nor (v_zero, v_zero);
+    v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
Index: gcc/testsuite/gcc.target/i386/20020531-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/20020531-1.c	(revision 120074)
+++ gcc/testsuite/gcc.target/i386/20020531-1.c	(working copy)
@@ -4,7 +4,7 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
 /* { dg-options "-O2 -mmmx" } */
 
-typedef unsigned char __v8qi __attribute__ ((vector_size (8)));
+typedef char __v8qi __attribute__ ((vector_size (8)));
 extern void abort (void);
 extern void exit (int);
 
Index: gcc/testsuite/gcc.dg/simd-5.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-5.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-5.c	(working copy)
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*incompatible types in initialization" } */
Index: gcc/testsuite/gcc.dg/simd-6.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-6.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-6.c	(working copy)
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*incompatible types in initialization" } */
Index: gcc/testsuite/gcc.dg/simd-1.c
===================================================================
--- gcc/testsuite/gcc.dg/simd-1.c	(revision 120074)
+++ gcc/testsuite/gcc.dg/simd-1.c	(working copy)
@@ -32,7 +32,7 @@ hanneke ()
   e = (typeof (e)) a;
 
   /* Different signed SIMD assignment.  */
-  f = a;
+  f = a; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*35: error: incompatible types in assignment" } */
 
   /* Casted different signed SIMD assignment.  */
   f = (uv4si) a;
Index: gcc/testsuite/g++.dg/conversion/simd1.C
===================================================================
--- gcc/testsuite/g++.dg/conversion/simd1.C	(revision 120074)
+++ gcc/testsuite/g++.dg/conversion/simd1.C	(working copy)
@@ -5,9 +5,9 @@
 
 #define vector __attribute__((vector_size(16)))
 
-vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "vld" } */
 /* { dg-warning "vector returned by ref" "" { target { powerpc*-*-linux* && ilp32 } }  8 } */
-vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "vld" } */
 
 extern int i;
 extern vector signed short vss;
@@ -17,7 +17,7 @@ extern const vector signed short *cvssp;
 
 void foo ()
 {
-  vss = vld(i, vscp);        /* { dg-error "no match" } */
+  vss = vld(i, vscp);        /* { dg-error "no matching function for call" } */
   vss = vld(i, vssp);
   vss = vld(i, cvssp);
 }
Index: gcc/testsuite/g++.dg/conversion/simd3.C
===================================================================
--- gcc/testsuite/g++.dg/conversion/simd3.C	(revision 120074)
+++ gcc/testsuite/g++.dg/conversion/simd3.C	(working copy)
@@ -10,6 +10,6 @@ unsigned int __attribute__((vector_size(
 void foo()
 {
 	b + d; /* { dg-error "invalid operands to binary" } */
-	d += e;
+	d += e; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*cannot convert 'unsigned int __vector__' to 'int __vector__' in assignment" } */
 	d2 += d;
 }
Index: gcc/testsuite/g++.dg/ext/attribute-test-2.C
===================================================================
--- gcc/testsuite/g++.dg/ext/attribute-test-2.C	(revision 120074)
+++ gcc/testsuite/g++.dg/ext/attribute-test-2.C	(working copy)
@@ -15,8 +15,8 @@ public:
      return (__attribute__((vector_size(16))) short) vec;
    }
 
-   operator __attribute__((vector_size(16))) int (void) {
-     return (__attribute__((vector_size(16))) int) vec1;
+   operator __attribute__((vector_size(16))) unsigned int (void) {
+     return (__attribute__((vector_size(16))) unsigned int) vec1;
    }
 
    vector_holder () {
@@ -30,6 +30,7 @@ public:
 union u {
               char f[16];
               vector unsigned int v;
+              vector short vs;
 } data;
 
 
@@ -37,10 +38,10 @@ vector_holder vh;
 
 int main()
 {
-  data.v = (__attribute__((vector_size(16))) short) vh;
+  data.vs = (__attribute__((vector_size(16))) short) vh;
   if (data.f[0] != 'a' || data.f[15] != 'd')
     abort(); 
-  data.v = (__attribute__((vector_size(16))) int) vh;
+  data.v = (__attribute__((vector_size(16))) unsigned int) vh;
   if (data.f[0] != 'm' || data.f[15] != 'p')
     abort(); 
 
Index: gcc/cp/typeck.c
===================================================================
--- gcc/cp/typeck.c	(revision 120074)
+++ gcc/cp/typeck.c	(working copy)
@@ -6218,7 +6218,7 @@ convert_for_assignment (tree type, tree 
   coder = TREE_CODE (rhstype);
 
   if (TREE_CODE (type) == VECTOR_TYPE && coder == VECTOR_TYPE
-      && vector_types_convertible_p (type, rhstype))
+      && vector_types_convertible_p (type, rhstype, true))
     return convert (type, rhs);
 
   if (rhs == error_mark_node || rhstype == error_mark_node)
@@ -6774,7 +6774,7 @@ ptr_reasonably_similar (tree to, tree fr
 	continue;
 
       if (TREE_CODE (to) == VECTOR_TYPE
-	  && vector_types_convertible_p (to, from))
+	  && vector_types_convertible_p (to, from, false))
 	return 1;
 
       if (TREE_CODE (to) == INTEGER_TYPE
Index: gcc/cp/call.c
===================================================================
--- gcc/cp/call.c	(revision 120074)
+++ gcc/cp/call.c	(working copy)
@@ -842,7 +842,7 @@ standard_conversion (tree to, tree from,
 	conv->rank = cr_promotion;
     }
   else if (fcode == VECTOR_TYPE && tcode == VECTOR_TYPE
-	   && vector_types_convertible_p (from, to))
+	   && vector_types_convertible_p (from, to, false))
     return build_conv (ck_std, to, conv);
   else if (!(flags & LOOKUP_CONSTRUCTOR_CALLABLE)
 	   && IS_AGGR_TYPE (to) && IS_AGGR_TYPE (from)
Index: gcc/c.opt
===================================================================
--- gcc/c.opt	(revision 120074)
+++ gcc/c.opt	(working copy)
@@ -571,6 +571,10 @@ Inject friend functions into enclosing n
 flabels-ok
 C++ ObjC++
 
+flax-vector-conversions
+C ObjC C++ ObjC++
+Allow implicit conversions between vectors with differing numbers of subparts and/or differing element types.
+
 fms-extensions
 C ObjC C++ ObjC++
 Don't warn about uses of Microsoft extensions
Index: gcc/c-typeck.c
===================================================================
--- gcc/c-typeck.c	(revision 120074)
+++ gcc/c-typeck.c	(working copy)
@@ -3870,7 +3870,7 @@ convert_for_assignment (tree type, tree 
     }
   /* Some types can interconvert without explicit casts.  */
   else if (codel == VECTOR_TYPE && coder == VECTOR_TYPE
-	   && vector_types_convertible_p (type, TREE_TYPE (rhs)))
+	   && vector_types_convertible_p (type, TREE_TYPE (rhs), true))
     return convert (type, rhs);
   /* Arithmetic types all interconvert, and enum is treated like int.  */
   else if ((codel == INTEGER_TYPE || codel == REAL_TYPE
@@ -4600,7 +4600,7 @@ digest_init (tree type, tree init, bool 
      below and handle as a constructor.  */
   if (code == VECTOR_TYPE
       && TREE_CODE (TREE_TYPE (inside_init)) == VECTOR_TYPE
-      && vector_types_convertible_p (TREE_TYPE (inside_init), type)
+      && vector_types_convertible_p (TREE_TYPE (inside_init), type, true)
       && TREE_CONSTANT (inside_init))
     {
       if (TREE_CODE (inside_init) == VECTOR_CST
Index: gcc/c-opts.c
===================================================================
--- gcc/c-opts.c	(revision 120074)
+++ gcc/c-opts.c	(working copy)
@@ -705,6 +705,10 @@ c_common_handle_option (size_t scode, co
       flag_implicit_templates = value;
       break;
 
+    case OPT_flax_vector_conversions:
+      flag_lax_vector_conversions = value;
+      break;
+
     case OPT_fms_extensions:
       flag_ms_extensions = value;
       break;
Index: gcc/c-common.c
===================================================================
--- gcc/c-common.c	(revision 120074)
+++ gcc/c-common.c	(working copy)
@@ -254,6 +254,10 @@ int flag_short_double;
 
 int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 int flag_ms_extensions;
 
@@ -1072,19 +1076,40 @@ check_main_parameter_types (tree decl)
    pedwarn ("%q+D takes only zero or two arguments", decl);
 }
 
- 
-/* Nonzero if vector types T1 and T2 can be converted to each other
-   without an explicit cast.  */
-int
-vector_types_convertible_p (tree t1, tree t2)
+/* True if vector types T1 and T2 can be converted to each other
+   without an explicit cast.  If EMIT_LAX_NOTE is true, and T1 and T2
+   can only be converted with -flax-vector-conversions yet that is not
+   in effect, emit a note telling the user about that option if such
+   a note has not previously been emitted.  */
+bool
+vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note)
 {
-  return targetm.vector_opaque_p (t1)
-	 || targetm.vector_opaque_p (t2)
-	 || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
-	     && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
-		 TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
-	     && INTEGRAL_TYPE_P (TREE_TYPE (t1))
-		== INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+  static bool emitted_lax_note = false;
+  bool convertible_lax =
+    targetm.vector_opaque_p (t1)
+    || targetm.vector_opaque_p (t2)
+    || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
+        && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
+           TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
+       && INTEGRAL_TYPE_P (TREE_TYPE (t1))
+          == INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+
+  if (!convertible_lax || flag_lax_vector_conversions)
+    return convertible_lax;
+
+  if (TYPE_VECTOR_SUBPARTS (t1) == TYPE_VECTOR_SUBPARTS (t2)
+      && comptypes (TREE_TYPE (t1), TREE_TYPE (t2)))
+    return true;
+
+  if (emit_lax_note && !emitted_lax_note)
+    {
+      emitted_lax_note = true;
+      inform ("use -flax-vector-conversions to permit "
+              "conversions between vectors with differing "
+              "element types or numbers of subparts");
+    }
+
+  return false;
 }
 
 /* Warns if the conversion of EXPR to TYPE may alter a value.
Index: gcc/c-common.h
===================================================================
--- gcc/c-common.h	(revision 120074)
+++ gcc/c-common.h	(working copy)
@@ -392,6 +392,10 @@ extern int flag_short_double;
 
 extern int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+extern int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 extern int flag_ms_extensions;
 
@@ -800,7 +804,7 @@ extern tree finish_label_address_expr (t
 extern tree lookup_label (tree);
 extern tree lookup_name (tree);
 
-extern int vector_types_convertible_p (tree t1, tree t2);
+extern bool vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note);
 
 extern rtx c_expand_expr (tree, rtx, enum machine_mode, int, rtx *);
 
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	(revision 120074)
+++ gcc/config/i386/i386.c	(working copy)
@@ -15911,7 +15911,7 @@ ix86_init_mmx_sse_builtins (void)
   const struct builtin_description * d;
   size_t i;
 
-  tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
+  tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
   tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
   tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
   tree V2DI_type_node
@@ -15920,7 +15920,7 @@ ix86_init_mmx_sse_builtins (void)
   tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
   tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
   tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
-  tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
+  tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
   tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
 
   tree pchar_type_node = build_pointer_type (char_type_node);
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c	(revision 120074)
+++ gcc/config/rs6000/rs6000-c.c	(working copy)
@@ -224,17 +224,17 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
@@ -242,17 +242,17 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
@@ -260,11 +260,11 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 
   /* Binary AltiVec builtins.  */
   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
@@ -578,31 +578,23 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
@@ -620,29 +612,29 @@ const struct altivec_builtin_types altiv
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
Index: gcc/config/rs6000/altivec.h
===================================================================
--- gcc/config/rs6000/altivec.h	(revision 120074)
+++ gcc/config/rs6000/altivec.h	(working copy)
@@ -332,7 +332,7 @@ NAME (T a1, U a2) \
 __altivec_binary_pred(vec_cmplt,
   __builtin_vec_cmpgt (a2, a1))
 __altivec_binary_pred(vec_cmple,
-  __builtin_altivec_cmpge (a2, a1))
+  __builtin_vec_cmpge (a2, a1))
 
 __altivec_scalar_pred(vec_all_in,
   __builtin_altivec_vcmpbfp_p (__CR6_EQ, a1, a2))
@@ -402,7 +402,7 @@ __altivec_scalar_pred(vec_any_nle,
 #undef __altivec_binary_pred
 #else
 #define vec_cmplt(a1, a2) __builtin_vec_cmpgt ((a2), (a1))
-#define vec_cmple(a1, a2) __builtin_altivec_vcmpgefp ((a2), (a1))
+#define vec_cmple(a1, a2) __builtin_vec_cmpge ((a2), (a1))
 
 #define vec_all_in(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ, (a1), (a2))
 #define vec_any_out(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ_REV, (a1), (a2))

Re: Stricter implicit conversions between vectors, revised patch

[Gerald Pfeifer]

On Sat, 23 Dec 2006, Mark Shinwell wrote:
> These have now been sorted.  This patch has no regressions on
> x86_64-unknown-linux-gnu and powerpc64-unknown-linux-gnu.  OK to apply?

If/when this goes in, would you mind adding something to 
gcc-4.3/changes.html as well describing the stricter behavior
and the new option?

Thanks,
Gerald

Re: Stricter implicit conversions between vectors, revised patch

[Mark Mitchell]

Mark Shinwell wrote:

> 2006-12-23  Mark Shinwell  <shinwell@codesourcery.com>
> 
>         gcc/
>         * c.opt: Add -flax-vector-conversions.
>         * c-typeck.c (convert_for_assignment): Pass flag to
>         vector_types_convertible_p to allow emission of note.
>         (digest_init): Likewise.
>         * c-opts.c: Handle -flax-vector-conversions.
>         * c-common.c (flag_lax_vector_conversions): New.
>         (vector_types_convertible_p): Unless -flax-vector conversions
>         has been passed, disallow conversions between vectors with
>         differing numbers of subparts and/or element types.  If such
>         a conversion is disallowed, possibly emit a note on the first
>         occasion only to inform the user of -flax-vector-conversions.
>         The new last argument specifies this.
>         * c-common.h (flag_lax_vector_conversions): New.
>         (vector_types_convertible_p): Add extra argument.
>         * config/i386/i386.c (ix86_init_mmx_sse_builtins): Use
>         char_type_node for V*QI type vectors.
>         * config/rs6000/rs6000-c.c (altivec_overloaded_builtins):
>         Update to satisfy new typechecking rules.
>         * config/rs6000/altivec.h (vec_cmple): Use vec_cmpge, for both
>     C and C++ variants.
>         * doc/invoke.texi (C Dialect Options): Document
>         -flax-vector-conversions.
> 
>         gcc/cp/
>         * call.c (standard_conversion): Pass flag to
>         vector_types_convertible_p to disallow emission of note.
>         * typeck.c (convert_for_assignment): Pass flag to
>         vector_types_convertible_p to allow emission of note.
>         (ptr_reasonably_similar): Pass flag to vector_types_convertible_p
>         to disallow emission of note.
> 
>         gcc/testsuite/
>         * gcc.target/i386/20020531-1.c: Use "char" not "unsigned char"
>         in __v8qi typedef.
>         * gcc.target/powerpc/altivec-vec-merge.c (foo): Add casts.
>         * gcc.dg/simd-1.c: Update dg-error directives to reflect new
>         compiler behaviour.
>         * gcc.dg/simd-5.c: Likewise.
>         * gcc.dg/simd-6.c: Likewise.
>         * g++.dg/conversion/simd1.C: Likewise.
>         * g++.dg/conversion/simd3.C: Likewise.
>         * g++.dg/ext/attribute-test-2.C (data): Add "vs" member.
>         (main): Use it.

OK, thanks.  Please be on the lookout for reports of failures on
architectures that you didn't test; there may be other tests lurking
that need editing to conform to the new rules.

Thanks,

-- 
Mark Mitchell
CodeSourcery
mark@codesourcery.com
(650) 331-3385 x713

Re: Stricter implicit conversions between vectors, revised patch

[Mark Shinwell]

Gerald Pfeifer wrote:
> On Sat, 23 Dec 2006, Mark Shinwell wrote:
>> These have now been sorted.  This patch has no regressions on
>> x86_64-unknown-linux-gnu and powerpc64-unknown-linux-gnu.  OK to apply?
> 
> If/when this goes in, would you mind adding something to 
> gcc-4.3/changes.html as well describing the stricter behavior
> and the new option?

Is this OK?

Mark

--


2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>

	* changes.html (C family): Describe new restrictions on
	implicit conversions between generic vector types.


Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.3/changes.html,v
retrieving revision 1.17
diff -U3 -r1.17 changes.html
--- changes.html        7 Jan 2007 05:00:08 -0000       1.17
+++ changes.html        8 Jan 2007 09:53:48 -0000
@@ -79,6 +79,23 @@

  <h3>C family</h3>

+  <ul>
+    <li>
+    Implicit conversions between generic vector types are now
+    only permitted when the two vectors in question have the same number
+    of elements and compatible element types.  (Note that the restriction
+    involves <em>compatible</em> element types, not
+    implicitly-convertible element types: thus, a vector type with element
+    type <code>int</code> may not be implicitly converted to a vector
+    type with element type <code>unsigned int</code>.)
+    This restriction, which is in line with specifications for SIMD
+    architectures such as AltiVec, may be relaxed using the
+    flag <code>-flax-vector-conversions</code>.
+    This flag is intended only as a compatibility measure and should not
+    be used for new code.
+    </li>
+  </ul>
+
  <h3>C++</h3>
    <ul>
      <li>Experimental support for the upcoming ISO C++ standard, C++0x,

Re: Stricter implicit conversions between vectors, revised patch

[Gerald Pfeifer]

On Mon, 8 Jan 2007, Mark Shinwell wrote:
> Is this OK?

Very nice description, thanks!

Gerald

Re: Stricter implicit conversions between vectors, revised patch

[Andrew Pinski]

[-- Attachment #1: Type: text/plain, Size: 586 bytes --]

On Wed, 2007-01-03 at 14:17 -0800, Mark Mitchell wrote:
> Mark Shinwell wrote:

> OK, thanks.  Please be on the lookout for reports of failures on
> architectures that you didn't test; there may be other tests lurking
> that need editing to conform to the new rules.

Since we know error out correctly.  I removed the xfail from
testsuite/gcc.target/spu/intrinsics-1.c which I added when I added the
testcase to test this specific problem with the intrinsics.

Committed after a build/test on spu-elf.

Thanks,
Andrew Pinski

ChangeLog:

	* gcc.target/spu/intrinsics-1.c: Remove xfail.

[-- Attachment #2: fixtestcase.diff.txt --]
[-- Type: text/x-patch, Size: 636 bytes --]

Index: testsuite/gcc.target/spu/intrinsics-1.c
===================================================================
--- testsuite/gcc.target/spu/intrinsics-1.c	(revision 120520)
+++ testsuite/gcc.target/spu/intrinsics-1.c	(working copy)
@@ -13,6 +13,5 @@ void f(void)
   gt = spu_cmpgt(a, a1); /* { dg-error "integer from pointer without a cast" } */
   gt = spu_cmpgt(a, b); /* { dg-error "parameter list" } */
   gt = spu_cmpgt(a, a);
-  /* Remove this xfail once, we reject implict conversions between vector types.  */
-  a = spu_cmpgt(a, a); /* { dg-error "" "" { xfail *-*-* } } */
+  a = spu_cmpgt(a, a); /* { dg-error "" } */
 }

Re: Stricter implicit conversions between vectors, revised patch

[Joseph S. Myers]

The vector conversions changes broke the handling of opaque types.  These 
are always meant to be convertible to/from other types of the same size, 
whether or not being lax (see the SPE PIM, which defines an opaque type 
and lots of non-opaque types), but not to/from types of different sizes.  
This showed up in spe.h failing to compile.  (PowerPC is the only target 
defining the hook to have opaque types at all.)

I've applied this patch after testing on powerpc-none-linux-gnuspe.

2007-01-11  Joseph Myers  <joseph@codesourcery.com>

	* c-common.c (vector_types_convertible_p): Treat opaque types as
	always convertible if they have the same size, but not otherwise.

Index: gcc/c-common.c
===================================================================
--- gcc/c-common.c	(revision 120682)
+++ gcc/c-common.c	(working copy)
@@ -1091,15 +1091,19 @@
 vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note)
 {
   static bool emitted_lax_note = false;
-  bool convertible_lax =
-    targetm.vector_opaque_p (t1)
-    || targetm.vector_opaque_p (t2)
-    || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
-        && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
-           TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
-       && INTEGRAL_TYPE_P (TREE_TYPE (t1))
-          == INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+  bool convertible_lax;
 
+  if ((targetm.vector_opaque_p (t1) || targetm.vector_opaque_p (t2))
+      && tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2)))
+    return true;
+
+  convertible_lax =
+    (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
+     && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
+	 TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
+     && (INTEGRAL_TYPE_P (TREE_TYPE (t1))
+	 == INTEGRAL_TYPE_P (TREE_TYPE (t2))));
+
   if (!convertible_lax || flag_lax_vector_conversions)
     return convertible_lax;
 

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: Stricter implicit conversions between vectors, revised patch

[Paolo Bonzini]

Joseph S. Myers wrote:
> The vector conversions changes broke the handling of opaque types.  These 
> are always meant to be convertible to/from other types of the same size, 
> whether or not being lax (see the SPE PIM, which defines an opaque type 
> and lots of non-opaque types), but not to/from types of different sizes.  
> This showed up in spe.h failing to compile.  (PowerPC is the only target 
> defining the hook to have opaque types at all.)

At one point, I had a patch to remove the hook at all, and instead use a 
bit in the vector type itself.  Would you be interested in me reviving it?

Thanks,

Paolo

Re: Stricter implicit conversions between vectors, revised patch

[Joseph S. Myers]

On Fri, 12 Jan 2007, Paolo Bonzini wrote:

> Joseph S. Myers wrote:
> > The vector conversions changes broke the handling of opaque types.  These
> > are always meant to be convertible to/from other types of the same size,
> > whether or not being lax (see the SPE PIM, which defines an opaque type and
> > lots of non-opaque types), but not to/from types of different sizes.  This
> > showed up in spe.h failing to compile.  (PowerPC is the only target defining
> > the hook to have opaque types at all.)
> 
> At one point, I had a patch to remove the hook at all, and instead use a bit
> in the vector type itself.  Would you be interested in me reviving it?

Depends on whether there's a spare bit available in vector types, but this 
seems reasonable in principle.

-- 
Joseph S. Myers
joseph@codesourcery.com