[PATCH] RISC-V: cost model for loading 64bit constant in rv32

["Sinan" <sinan.lin@linux.alibaba.com>]

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loading constant 0x739290001LL in rv32 can be done with three instructions
output:
li a1, 7
lui a1, 234128
addi a1, a1, 1
Similarly, loading 0x839290001LL in rv32 can be done within three instructions
expected output:
li a1, 8
lui a1, 234128
addi a1, a1, 1
However, riscv_build_integer does not handle this case well and makes a wrong prediction about the number of instructions needed and then the constant is forced to put in the memory via riscv_const_insns and emit_move_insn.
real output:
lui a4,%hi(.LC0)
lw a2,%lo(.LC0)(a4)
lw a3,%lo(.LC0+4)(a4)
.LC0:
 .word958988289
 .word8
comparison with clang:
https://godbolt.org/z/v5nxTbKe9 <https://godbolt.org/z/v5nxTbKe9 >

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From eb1b8386e62ed326618105358b9e68fe3ac86722 Mon Sep 17 00:00:00 2001
From: Sinan Lin <sinan.lin@linux.alibaba.com>
Date: Wed, 9 Nov 2022 10:46:14 +0800
Subject: [PATCH] riscv: improve cost model for loading 64bit constant in rv32.

64bit constant like 0x839290001LL can be loaded within three
instructions in rv32

  li      a1, 8
  lui     a1, 234128
  addi    a1, a1, 1

However, the cost model doesn't not handle this case well, and
leads to a suboptimal codegen:

  lui     a4,%hi(.LC0)
  lw      a2,%lo(.LC0)(a4)
  lw      a3,%lo(.LC0+4)(a4)
---
 gcc/config/riscv/riscv.cc                     | 23 ++++++++++++
 .../riscv/rv32-load-64bit-constant.c          | 35 +++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rv32-load-64bit-constant.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32f9ef9ade9..9dffabdc5e3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -618,6 +618,29 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value,
 	}
     }
 
+  if ((value > INT32_MAX || value < INT32_MIN) && !TARGET_64BIT)
+    {
+      unsigned HOST_WIDE_INT loval = sext_hwi (value, 32);
+      unsigned HOST_WIDE_INT hival = sext_hwi ((value - loval) >> 32, 32);
+      struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS],
+			    hicode[RISCV_MAX_INTEGER_OPS];
+      int hi_cost, lo_cost;
+
+      hi_cost = riscv_build_integer_1 (hicode, hival, mode);
+      if (hi_cost < cost)
+	{
+	  lo_cost = riscv_build_integer_1 (alt_codes, loval, mode);
+	  if (lo_cost + hi_cost < cost)
+	    {
+	      memcpy (codes, alt_codes,
+			  lo_cost * sizeof (struct riscv_integer_op));
+	      memcpy (codes + lo_cost, hicode,
+			  hi_cost * sizeof (struct riscv_integer_op));
+	      cost = lo_cost + hi_cost;
+	    }
+	}
+    }
+
   return cost;
 }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rv32-load-64bit-constant.c b/gcc/testsuite/gcc.target/riscv/rv32-load-64bit-constant.c
new file mode 100644
index 00000000000..a3936a8f6b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rv32-load-64bit-constant.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc -mabi=ilp32 -Os" } */
+
+extern unsigned long long movdi;
+void
+rv32_mov_64bit_int1 (void)
+{
+  movdi = 0x739290001LL;
+}
+
+void
+rv32_mov_64bit_int2 (void)
+{
+  movdi = 0x839290001LL;
+}
+
+void
+rv32_mov_64bit_int3 (void)
+{
+  movdi = 0x3929000139290000LL;
+}
+
+void
+rv32_mov_64bit_int4 (void)
+{
+  movdi = 0x3929001139290000LL;
+}
+
+void
+rv32_mov_64bit_int5 (void)
+{
+  movdi = 0x14736def39290000LL;
+}
+
+/* { dg-final { scan-assembler-not "\.LC\[0-9\]" } } */
-- 
2.19.1.6.gb485710b