From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71515 invoked by alias); 20 Dec 2018 01:12:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 71502 invoked by uid 89); 20 Dec 2018 01:12:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_NUMSUBJECT,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=H*r:0800, H*UA:6.1, H*u:6.1 X-HELO: huawei.com Received: from szxga04-in.huawei.com (HELO huawei.com) (45.249.212.190) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 20 Dec 2018 01:12:42 +0000 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 0935E298882F1; Thu, 20 Dec 2018 09:12:37 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.408.0; Thu, 20 Dec 2018 09:12:28 +0800 Subject: Re: [PATCH] [aarch64] Revert support for ARMv8.2 in tsv110 To: "Richard Earnshaw (lists)" , References: <1545189093-47026-1-git-send-email-zhangshaokun@hisilicon.com> <208e2e40-06bb-ac8a-6464-9c1ab4144e47@arm.com> CC: , , , , , From: Zhangshaokun Message-ID: <4627f464-aec8-a86e-e0be-09fd4051a3f5@hisilicon.com> Date: Thu, 20 Dec 2018 01:12:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <208e2e40-06bb-ac8a-6464-9c1ab4144e47@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2018-12/txt/msg01432.txt.bz2 Hi Richard, On 2018/12/19 18:12, Richard Earnshaw (lists) wrote: > On 19/12/2018 03:11, Shaokun Zhang wrote: >> For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but >> some mandatory features are not implemented. Revert to ARMv8.2 that >> all mandatory features are supported. >> > > Thanks, I've put this in. > Thanks. > I've modified the ChangeLog entry slightly - we normally use 'revert' in > the specific sense of completely removing an existing patch. > I have checked the modified ChangeLog that is precise. Thanks for more explanation about 'revert', got it. > Also, when sending patches, please do not send ChangeLog entries as part > of the patch file. Because the file is always updated at the head, the > patch hunk is rarely going to apply cleanly. Instead, include the > ChangeLog text as part of your email description; that way we can then Surely, I will follow it. At the beginning, I also had the doubt that every one would update the ChangeLog when he upstreamed the patch, how to apply the patch directly if the ChangeLog file is conflicted. I have understood it when you given the detailed description. Thanks, Shaokun > paste it directly into the ChangeLog file itself and simply correct the > date. > > R. > >> --- >> gcc/ChangeLog | 5 +++++ >> gcc/config/aarch64/aarch64-cores.def | 6 +++--- >> 2 files changed, 8 insertions(+), 3 deletions(-) >> >> diff --git a/gcc/ChangeLog b/gcc/ChangeLog >> index e9f5baa6557c..842876b0ae90 100644 >> --- a/gcc/ChangeLog >> +++ b/gcc/ChangeLog >> @@ -1,3 +1,8 @@ >> +2018-12-19 Shaokun Zhang >> + >> + * config/aarch64/aarch64-cores.def (tsv110) : Revert support for ARMv8.2 >> + in tsv110. >> + >> 2018-12-18 Vladimir Makarov >> >> PR rtl-optimization/87759 >> diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def >> index 74be5dbf2595..20f4924e084d 100644 >> --- a/gcc/config/aarch64/aarch64-cores.def >> +++ b/gcc/config/aarch64/aarch64-cores.def >> @@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 >> AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) >> AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1) >> >> -/* ARMv8.4-A Architecture Processors. */ >> - >> /* HiSilicon ('H') cores. */ >> -AARCH64_CORE("tsv110", tsv110, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) >> +AARCH64_CORE("tsv110", tsv110, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) >> + >> +/* ARMv8.4-A Architecture Processors. */ >> >> /* Qualcomm ('Q') cores. */ >> AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) >> > > > . >