Index: config/mips/mips.h =================================================================== --- config/mips/mips.h (revision 125997) +++ config/mips/mips.h (working copy) @@ -136,6 +136,10 @@ extern const struct mips_cpu_info mips_c extern const struct mips_cpu_info *mips_arch_info; extern const struct mips_cpu_info *mips_tune_info; extern const struct mips_rtx_cost_data *mips_cost; + +extern bool mips_builtin_clear_cache_inline_p (void); +#undef TARGET_BUILTIN_CLEAR_CACHE_INLINE_P +#define TARGET_BUILTIN_CLEAR_CACHE_INLINE_P mips_builtin_clear_cache_inline_p #endif /* Macros to silence warnings about numbers being signed in traditional @@ -770,6 +774,10 @@ extern const struct mips_rtx_cost_data * || ISA_MIPS32R2 \ || ISA_MIPS64 \ || TARGET_MIPS5500) + +/* ISA includes synci, jr.hb and jalr.hb */ +#define ISA_HAS_SYNCI ISA_MIPS32R2 + /* Add -G xx support. */ @@ -2108,6 +2116,17 @@ typedef struct mips_args { #define CACHE_FLUSH_FUNC "_flush_cache" #endif +/* Clear the instruction cache from `beg' to `end'. */ +#undef CLEAR_INSN_CACHE +#define CLEAR_INSN_CACHE(BEG, END) \ +{ \ + extern void _flush_cache (char *b, int l, int f); \ + if (__builtin_clear_cache_inline_p()) \ + __builtin___clear_cache ((BEG), (END)); \ + else \ + _flush_cache ((BEG), ((char *)(END) - (char *)(BEG)), 3); \ +} + /* A C statement to initialize the variable parts of a trampoline. ADDR is an RTX for the address of the trampoline; FNADDR is an RTX for the address of the nested function; STATIC_CHAIN is an @@ -2122,15 +2141,7 @@ typedef struct mips_args { chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \ emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \ emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \ - \ - /* Flush both caches. We need to flush the data cache in case \ - the system has a write-back cache. */ \ - /* ??? Should check the return value for errors. */ \ - if (mips_cache_flush_func && mips_cache_flush_func[0]) \ - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ - 0, VOIDmode, 3, ADDR, Pmode, \ - GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ - GEN_INT (3), TYPE_MODE (integer_type_node)); \ + emit_insn (gen_flush_icache (copy_rtx (ADDR), GEN_INT (TRAMPOLINE_SIZE))); \ } /* Addressing modes, and classification of registers for them. */ Index: config/mips/netbsd.h =================================================================== --- config/mips/netbsd.h (revision 125997) +++ config/mips/netbsd.h (working copy) @@ -190,6 +190,16 @@ Boston, MA 02110-1301, USA. */ #undef CACHE_FLUSH_FUNC #define CACHE_FLUSH_FUNC "_cacheflush" +/* Clear the instruction cache from `beg' to `end'. */ +#undef CLEAR_INSN_CACHE +#define CLEAR_INSN_CACHE(BEG, END) \ +{ \ + extern void _cacheflush (char *b, int l, int f); \ + if (__builtin_clear_cache_inline_p()) \ + __builtin___clear_cache ((BEG), (END)); \ + else \ + _cacheflush ((BEG), ((char *)(END) - (char *)(BEG)), 3); \ +} /* Make gcc agree with */ Index: config/mips/mips-protos.h =================================================================== --- config/mips/mips-protos.h (revision 125997) +++ config/mips/mips-protos.h (working copy) @@ -1,6 +1,6 @@ /* Prototypes of target machine for GNU compiler. MIPS version. Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. + 1999, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and @@ -185,6 +185,7 @@ extern void mips_expand_call (rtx, rtx, extern void mips_emit_fcc_reload (rtx, rtx, rtx); extern void mips_set_return_address (rtx, rtx); extern bool mips_expand_block_move (rtx, rtx, rtx); +extern void mips_expand_synci_loop (rtx, rtx); extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx); extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, Index: config/mips/mips.md =================================================================== --- config/mips/mips.md (revision 125997) +++ config/mips/mips.md (working copy) @@ -50,6 +50,10 @@ (define_constants (UNSPEC_TLS_GET_TP 28) (UNSPEC_MFHC1 31) (UNSPEC_MTHC1 32) + (UNSPEC_CLEAR_HAZARD 33) + (UNSPEC_RDHWR 34) + (UNSPEC_SYNCI 35) + (UNSPEC_SYNC 36) (UNSPEC_ADDRESS_FIRST 100) @@ -4171,6 +4175,82 @@ (define_insn "cprestore" } [(set_attr "type" "store") (set_attr "length" "4,12")]) + +;; Flush the instruction cache starting as operands[0] with length +;; operands[1]. +(define_expand "flush_icache" + [(match_operand:SI 0 "pmode_register_operand") + (match_operand:SI 1 "register_operand")] + "" + " +{ + if (ISA_HAS_SYNCI) + { + rtx end_addr = gen_reg_rtx (Pmode); + emit_insn (gen_rtx_SET (VOIDmode, end_addr, + gen_rtx_PLUS (Pmode, operands[0], operands[1]))); + emit_insn (gen_clear_cache (operands[0], end_addr)); + } + else + /* Flush both caches. We need to flush the data cache in case + the system has a write-back cache. */ + if (mips_cache_flush_func && mips_cache_flush_func[0]) + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), + 0, VOIDmode, 3, operands[0], Pmode, + operands[1], TYPE_MODE (integer_type_node), + GEN_INT (3), TYPE_MODE (integer_type_node)); + DONE; +}") + +;; Expand in-line code to clear the instruction cache between operand[0] and +;; operand[1]. +(define_expand "clear_cache" + [(match_operand:SI 0 "general_operand") + (match_operand:SI 1 "general_operand")] + "ISA_HAS_SYNCI" + " +{ + mips_expand_synci_loop (operands[0], operands[1]); + emit_insn (gen_clear_hazard ()); + DONE; +}") + +(define_insn "sync" + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] + "" + "sync" + [(set_attr "length" "4")]) + +(define_insn "synci" + [(unspec_volatile [(match_operand:SI 0 "general_operand" "d")] UNSPEC_SYNCI)] + "" + "synci\t0(%0)" + [(set_attr "length" "4")]) + +(define_insn "rdhwr" + [(set (match_operand:SI 0 "general_operand" "=d") + (unspec_volatile [(match_operand:SI 1 "immediate_operand" "n")] + UNSPEC_RDHWR))] + "" + "rdhwr\t%0,$%1" + [(set_attr "length" "4")]) + +(define_insn "clear_hazard" + [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) + (clobber (reg:SI 31))] + "ISA_HAS_SYNCI" +{ + return ".set\tpush\n" + "\t.set\tnoreorder\n" + "\t.set\tnomacro\n" + "\tbal\t1f\n" + "\tnop\n" + "1:\taddiu\t$31,$31,12\n" + "\tjr.hb\t$31\n" + "\tnop\n" + "\t.set\tpop"; +} + [(set_attr "length" "20")]) ;; Block moves, see mips.c for more details. ;; Argument 0 is the destination Index: config/mips/mips.c =================================================================== --- config/mips/mips.c (revision 125997) +++ config/mips/mips.c (working copy) @@ -3759,6 +3759,47 @@ mips_block_move_loop (rtx dest, rtx src, mips_block_move_straight (dest, src, leftover); } + +/* Return true if we will expand __builtin_clear_cache() in-line. */ +bool +mips_builtin_clear_cache_inline_p (void) +{ + return ISA_HAS_SYNCI; +} + +/* Expand a loop of synci insns */ +void +mips_expand_synci_loop (rtx begin, rtx end) +{ + rtx end_addr, inc, label, label_ref, cmp, cmp_result; + + begin = force_reg(Pmode, begin); + end = force_reg(Pmode, end); + + /* Load INC with the cache line size (rdhwr INC,$1). */ + inc = gen_reg_rtx (SImode); + emit_insn (gen_rdhwr (inc ,gen_rtx_CONST_INT(SImode, 1))); + + /* Loop back to here. */ + label = gen_label_rtx (); + emit_label (label); + + emit_insn (gen_synci (begin)); + + cmp = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (VOIDmode, cmp, gen_rtx_GTU (Pmode, begin, end))); + + emit_insn (gen_rtx_SET (VOIDmode, begin, gen_rtx_PLUS (Pmode, begin, inc))); + + label_ref = gen_rtx_LABEL_REF (VOIDmode, label); + cmp_result = gen_rtx_EQ (VOIDmode, cmp, gen_rtx_CONST_INT(SImode, 0)); + emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, + gen_rtx_IF_THEN_ELSE (VOIDmode, cmp_result, + label_ref, + pc_rtx))); + emit_insn (gen_sync ()); +} + /* Expand a movmemsi instruction. */ bool Index: testsuite/gcc.target/mips/clear-cache-1.c =================================================================== --- testsuite/gcc.target/mips/clear-cache-1.c (revision 0) +++ testsuite/gcc.target/mips/clear-cache-1.c (revision 0) @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O2 -mips32r2" } */ +/* { dg-final { scan-assembler "synci" } } */ +/* { dg-final { scan-assembler "jr.hb" } } */ +/* { dg-final { scan-assembler-not "__clear_cache" } } */ + +void f() +{ + int size = 40; + char *memory = __builtin_alloca(size); + __builtin___clear_cache(memory, memory + size); +} + Index: testsuite/gcc.target/mips/clear-cache-2.c =================================================================== --- testsuite/gcc.target/mips/clear-cache-2.c (revision 0) +++ testsuite/gcc.target/mips/clear-cache-2.c (revision 0) @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O2 -mips32" } */ +/* { dg-final { scan-assembler-not "synci" } } */ +/* { dg-final { scan-assembler-not "jr.hb" } } */ +/* { dg-final { scan-assembler "__clear_cache" } } */ + +void f() +{ + int size = 40; + char *memory = __builtin_alloca(size); + __builtin___clear_cache(memory, memory + size); +} +