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From: David Ung <davidu@mips.com>
To: Sandra Loosemore <sandra@codesourcery.com>,
	  GCC Patches <gcc-patches@gcc.gnu.org>,
	 David Ung <davidu@mips.com>,
	 richard@codesourcery.com
Subject: Re: PATCH:  MIPS 74K load/store scheduling tweak (take 2)
Date: Mon, 06 Aug 2007 16:21:00 -0000	[thread overview]
Message-ID: <46B74A75.8070905@mips.com> (raw)
In-Reply-To: <87d4y3da61.fsf@firetop.home>

Richard Sandiford wrote:
> Sandra Loosemore <sandra@codesourcery.com> writes:
>> + /* Conditionally swap the instructions at POS1 and POS2 in ready queue
>> +    READY, also adjusting the priority of the instruction formerly at
>> +    POS1 when we do so.  */
>> + 
>> + static void
>> + mips_maybe_swap_ready (rtx *ready, int pos1, int pos2)
>> + {
>> +   if (pos1 < pos2
>> +       && INSN_PRIORITY (ready[pos1]) + 4 >= INSN_PRIORITY (ready[pos2]))
>> +     {
>> +       rtx temp;
>> +       INSN_PRIORITY (ready[pos1]) = INSN_PRIORITY (ready[pos2]);
>> +       temp = ready[pos1];
>> +       ready[pos1] = ready[pos2];
>> +       ready[pos2] = temp;
>> +     }
>> + }
> 
> To be a general function rather than a 74k function, the magic value
> 4 should be a parameter too.  The comment seems a bit vague: how about
> "Make sure the instruction at POS1 in ready queue READY is ahead of
> the instruction at POS2, but only if its priority is no less than
> LIMIT units of the other instruction's priority.  Assume that
> only one of the instructions may issue this cycle."  Copy-edit
> as necessary.
> 
> It isn't obvious without the last bit why you're only swapping,
> rather than inserting POS1 directly ahead of POS2.  With the
> comment there, you can remove:
> 
> +   /* At this point the ready queue may no longer be sorted, but that's
> +      OK since 74k can't schedule concurrent load/store on the same
> +      cycle.  */
> 
> I'm uncertain whether setting INSN_PRIORITY is really the
> right thing to do here.  David, why isn't the sorting done by
> mips_sched_reorder enough?
> 

This is the multi-issue problem.  ready_sort is called more than once during 
each cycle.  The 1st instruction chosen during that cycle may not be an AGEN one 
(eg a floating point insn or an ALU insn), which means mips_sched_reorder2 needs 
to be implemented.  So instead of doing the same thing in mips_sched_reorder2, 
just changing the INSN_PRIORITY gets the same effect done automatically by 
ready_sort.

David.

  reply	other threads:[~2007-08-06 16:21 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-08-04  0:13 Sandra Loosemore
2007-08-04  7:35 ` Richard Sandiford
2007-08-06 16:21   ` David Ung [this message]
2007-08-06 16:40     ` Richard Sandiford
2007-08-06 17:19       ` David Ung
2007-08-06 17:53         ` Richard Sandiford
2007-08-07 10:43           ` David Ung
2007-08-10 15:17       ` Sandra Loosemore
2007-08-10 15:22         ` Richard Sandiford
2007-08-10 16:37           ` Sandra Loosemore

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