From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13983 invoked by alias); 21 Aug 2007 10:34:27 -0000 Received: (qmail 13876 invoked by uid 22791); 21 Aug 2007 10:34:27 -0000 X-Spam-Check-By: sourceware.org Received: from dmz.mips-uk.com (HELO dmz.mips-uk.com) (194.74.144.194) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 21 Aug 2007 10:34:25 +0000 Received: from internal-mx1 ([192.168.192.240] helo=ukservices1.mips.com) by dmz.mips-uk.com with esmtp (Exim 3.35 #1 (Debian)) id 1INQxv-0003jZ-00; Tue, 21 Aug 2007 11:28:03 +0100 Received: from southgate.mips.com ([192.168.192.171]) by ukservices1.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1INQxm-0001cA-00; Tue, 21 Aug 2007 11:27:54 +0100 Message-ID: <46CABE2A.2090406@mips.com> Date: Tue, 21 Aug 2007 10:34:00 -0000 From: Nigel Stephens User-Agent: IceDove 1.5.0.12 (X11/20070606) MIME-Version: 1.0 To: Sandra Loosemore , GCC Patches , Nigel Stephens , Guy Morrogh , David Ung , Thiemo Seufer , Mark Mitchell , richard@codesourcery.com Subject: Re: PATCH: fine-tuning for can_store_by_pieces References: <46C3343A.5080407@codesourcery.com> <87ps1nop2x.fsf@firetop.home> <46C778D6.5060808@codesourcery.com> <87y7g6r50c.fsf@firetop.home> <46CA222D.2050107@codesourcery.com> <87ps1h5mda.fsf@firetop.home> In-Reply-To: <87ps1h5mda.fsf@firetop.home> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-MIPS-Technologies-UK-MailScanner: Found to be clean X-MIPS-Technologies-UK-MailScanner-From: nigel@mips.com X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2007-08/txt/msg01341.txt.bz2 Richard Sandiford wrote: > Sandra Loosemore writes: > >> OK, but what I was really asking was, is there a way to *test* for >> situations where we should generate the lui/ori/sw sequences instead >> of the lw/sw? Some combination of TARGET_foo flags and/or the size of >> the string? >> > > Well, I suppose: > > !optimize_size && !TARGET_MIPS16 && mips_issue_rate () > 1 > > Many MIPS dual-issue processors are asymettric, and may be able to issue lui, ori and sw down only one pipe or the other -- not both in parallel. So I don't think that testing mips_issue_rate() is sufficient. Nigel